DESIGN OF AN ALL-DIGITAL PLL (ADPLL)
CORE ON FPGA
Sandeep Vallabhanenia, Dr. Sanjay Attrib, N. Krishnanc,
Sanjay Sharmad, R. C. Chauhane
a
Sci./Engr. SC, AISG/AISD, IISU, ISRO, Vattiyoorkavu, Trivandrum, Kerala, India
Asst. Prof, Dept. of ECE, NITTTR, Chandigarh-160019, PU, India
c
Sci./Engr. SF, AISG/AISD, IISU, ISRO, Vattiyoorkavu, Trivandrum, Kerala, India
d
Asst. Prof, Dept. of ECE, TIET, Patiala, Punjab, India
e
Director, SLIET, Longowal, Punjab, India
b
Abstract
A design of an All-Digital Phase Locked Loop (ADPLL) IP core using an accumulator
type DCO is proposed in order to generate desired frequency signals. Traditionally,
digital signal processing (DSP) algorithms were implemented using general-purpose
(programmable) DSP chips for low-rate applications, or special-purpose (fixed function)
DSP chip-sets and application-specific integrated circuits (ASICs) for higher rates.
Advancements in FPGAs provide new options for DSP design engineers. The FPGA
maintains the advantages of custom functionality like an ASIC while avoiding the high
development costs and the inability to make design modifications after production. If
excellent platforms like FPGA have the support of predefined and pre-verified IP cores,
the concept of 24 hour system on chip is very much possible. The current design of
ADPLL IP core is meant for this very purpose. Analog PLLs are in wide use in
Television, Radio, Pager, Telephony, Servo Motor control and several other areas.
Advances in Telecommunication, Wireless & Wire line, and Intelligent Network
concepts is posing greater demand towards design of PLLs. Faster and efficient operation
of PLLs is very much desired. Implementation of a digital PLL on a FPGA helps to
control the jitter involved in the operation of PLLs to a greater extent that is troubling the
current communication industry.
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I. Introduction
Complexities involved in SoC design can be reduced by ready to use IP cores.
Field Programmable Gate Arrays (FPGAs) have got excellent advantages such as high
reprogrammability, CAD tool support, faster design cycles and also their cost is going
down day by day [1]. Several DSP designs are getting increasingly realized onto FPGAs
due to this. In this regard, the present work aims at describing the design of an All Digital
Phase Locked Loop (ADPLL) IP Core using Xilinx ISE CAD tool and Xilinx
Virtex/Spartan FPGAs were used.
A Phase Locked Loop is a closed-loop control system that is used for the purpose
of synchronization of the phase and frequency with that of an incoming signal. Analog
PLLs are in wide use in Television, Radio, Pager, Telephony, Servo Motor control and
several other areas. Advances in Telecommunication, Wireless & Wire line, and
Intelligent Network concepts is posing greater demand towards design of PLLs. Faster
and efficient operation of PLLs is very much desired. Implementation of a digital PLL on
an FPGA helps to control the jitter involved in the operation of PLLs to a greater extent
that is troubling the current communication industry [2].
In addition to addressing the above-mentioned aspects, the main objective of the
current work, “IP Core Design Using Xilinx FPGA”, is to implement the ALL Digital
Phase Locked Loop (ADPLL) as a ready to use IP core on a Xilinx FPGA [3]. IP core
based design is an effective way to deal with shorter design times, more complex system
design and also gives excellent reusability. Achieving the above said requires the
extensive utilization of CAD tools for VHDL design, Simulation, Implementation and
final Place and Route on to the FPGA device. Hence, Implementing the DPLL as an IP
core makes the task of system designers of more complex work, especially in the above
mentioned application areas, much simplified.
II. ADPLL Components
A Phase Locked Loop is a closed loop control system which is used for the
purpose of synchronization of the frequency and phase of a locally generated signal with
that of an incoming signal. There are basically three components in a PLL. The Phase and
Frequency detector (PFD), the loop filter and the Voltage Controlled Oscillator (VCO).
The VCO is the heart of any PLL. The mechanism by which this VCO operates decides
the type of the PLL circuit being used. There are basically four types of constructing
PLLs:
1.
2.
3.
4.
Linear PLL(LPLL)
Digital PLL(DPLL)
All Digital PLL(ADPLL)
Software PLL(SPLL)
The analog PLL or the Linear PLL has been in use since a long time. It basically uses
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a multiplier circuit for serving the purpose of the PFD and a first order filter for the loop
filter and a typical analog VCO. Though the name Digital is present in the DPLL, it’s not
exactly a complete Digital PLL. The All Digital PLL makes an attempt at digitizing all
the three components required for the operation of a phase locked loop.
a) All Digital Phase Detector
The PD was the only component that was digitized long back. It’s used in the Digital
PLL. Similar idea can be extended to the ADPLL. The three common implementations of
the digital PD are:
1. Exclusive-or (EXOR) Gate
2. Edge triggered JK Flip-Flop
3. Digital Phase-Frequency Detector
Figure 1: XOR Implementation of a Phase & Frequency Detector
The EXOR mechanism offers a simple yet reliable method of phase detection. One
main drawback of this mechanism is its lack of sensitivity to edges. It’s a flat triggered
mechanism. To eliminate this drawback the edge triggered mechanism comes into
picture. The edge triggered JK mechanism is the most popular and effective one. It is
sensitive to the edges and hence instantaneous corrective action can be achieved. The
incoming reference signal acts as one input and the out put of the Digital Controlled
Oscillator (feedback of the PLL) acts as the other input. This edge triggering mechanism
has been used in the design of the current Jitter bounded ADPLL.
Figure 2: Edge Triggering Mechanism
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Using the above shown edge triggering mechanism a logical extension can be done to
the simple JK flip-flop such that it is sensitive to the edges and the clock can be
eliminated. As shown in the figure 3, the reference signal u1 and the output (or scaleddown output) signal u2 of the DCO are binary-valued signals. They are used to set or
reset an edge triggered JK flip-flop. The time period in which the Q output of the flipflop is a logic 1 is proportional to the phase error e. The Q signal is used to gate the
high-frequency clock signal into the counter. The counter is reset on every positive edge
of the u1 signal. The content N of the counter is also proportional to the phase error e,
where N is the n-bit output of this type of phase detector. The frequency of the highfrequency clock is usually Mf0, where f0 is the frequency of the reference signal and M is
a large positive integer.
U1
J
Enable
Counter
Q
U2
K
N
Clock
High frequency clock
Figure 3: Edge Triggered JK Phase Detector
The third type of phase detector is the combination of a tri-state phase-frequency
detector and a charge pump and it makes a very effective combination for acting as a
digital phase detector. But due to the analog components involved in the charge pump, it
is not being realized in the current design process. But many DPLL ICs make use of this
phase detector.
Figure 4: Phase Frequency Detector with charge pump
b) All Digital Loop Filter
There are two most important types of digital loop filters.
1. Up/Down counter loop filter
2. K Counter loop filter
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The digital filter is not always present in phase locked loops. But in higher order
loops where applications such as servo control, Telecommunications are involved the
digital loop filter is necessary. Different Phase Detectors generate different types of
signals. The simplest phase detector can be built from an Up/Down Counter.
UP
Clock
UP/DOWN
COUNTER
UP/DN
Pulse Forming
Circuit
From PD
DN
N
Figure 5: UP/Down Counter Loop Filter
It is easily adapted to operate in conjunction with an XOR or JK-flipflop phase
detectors and others. As shown in Fig 5, a pulse forming network is needed which
converts the incoming UP and DN pulses into a counting clock and a direction (UP/DN)
signal. On each UP pulse generated by the phase detector, the content N of the
UP/DOWN counter is incremented by 1. A DOWN pulse will decrement N in the same
manner. The content N is given by the n-bit parallel output signal Uf of the loop filter.
One of the most important digital loop filters is the K counter shown in Fig 6. This
loop filter always works together with the EXOR or the JK-flipflop phase detector.
Modulus Control
K Clock
UP Counter
Carry
UP/DN
Down Counter
Barrow
Figure 6: K Counter loop filter
The K counter consists of two independent counters, which are usually referred to as
“UP-counter” and “DOWN-counter”. In reality, however, both counters are always
counting upward. K is the modulus of both counters; that is, the contents of both counters
are in a range from 0 . . . k-1. K can be controlled by the K modulus control input and is
always an integer power of 2. The frequency of the clock signal (K clock) is by definition
M times the center frequency f0 of the ADPLL, where M is typically 8, 16, 32 . . . The
operation of the K counter is controlled by the DN/UP signal. If this signal is high, the
“DN-counter” is active, while the contents of the UP-counter stay frozen. In the opposite
case, the “UP-counter” counts up but the DN-counter stay frozen. Both counters recycle
to 0 when the contents exceed K-1. The most significant bit of the “UP-counter” is used
as a “carry” output, and the most significant bit of the “DN-counter” is used as a
“borrow” output. Consequently, the carry is high when the content of the UP-counter is
equal to or more than K/2. In analogy, the borrow output gets high when the content of
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the DN-counter is equal to or more than K/2. The positive-going edges of the carry and
borrow signals are used to control the frequency of a digitally controlled oscillator.
c). Digital-Controlled Oscillators
A variety of DCOs can be designed. The current design makes used of an
accumulator type DCO. The following DCO types are discussed:
1. Divide by N Counter DCO
2. Accumulator Type DCO
The simplest solution is the ÷N counter DCO. A ÷N counter is used to scale down the
signal generated by a high-frequency oscillator operating at a high frequency. The N-bit
parallel output signal of a digital loop filter is used to control the scaling factor N of the
÷N counter.
N mod control
From loop filter
out
÷N Counter
Fixed high-frequency oscillator
Figure 7: ÷N Counter DCO
The main limitation of the ÷N Counter DCO is that it does not offer a jitter design
criterion. That is, choice of a predefined jitter and tuning the ADPLL design based on
desirable precision requirements is not possible in the case of a ÷N Counter DCO. The
next and most important DCO is the accumulator-type DCO. Classical DPLLs used
VCOs but not a complete digital system. Digital versions of the Phase Detectors are
around since long but the digital versions of VCOs are difficult to design and also
meeting the flexibility of the existing VCOs has become a challenge. The accumulatortype DCO is the heart of the Jitter bounded ADPLL that is designed in this thesis work.
This is the first ever mechanism which leads to a complete All Digital PLL. The design
process starts with the choice of a predefined jitter requirement. The number of bits for
internal computations of errors and accumulation is chosen based on this jitter
requirement itself. The jitter bounded ADPLL design, the accumulator-type DCO and
their physical implementation are discussed in detail in the coming sections [4].
III. All Digital PLL with Jitter Bounded
a) General Structure
In its general form a DPLL consists mainly of a frequency generator (DCO), phasefrequency comparator, and a filter interconnect as shown in the figure [5].
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fs
fref
÷q
fDCO
fref/q
fDCO/p
÷p
Phase
Compa
rator
LPF
DCO
Figure 8: General Structure of a DPLL
A reference clock f ref is divided by an integer q, producing a signal
f ref
to which the
q
DCO is to be locked. The function of the DCO is to generate a range of frequencies from
a system clock which operate at a frequency fs, much higher than the DCO output
frequency f DCO . Before being fed back to the phase-frequency comparator, the DCO
f
output is divided by an integer p, so that the frequency DCO is actually compared
p
f ref
with
. The result of this comparison is low pass filtered and fed back to the DCO,
q
which adjusts the output frequency to reduce the error. The low-pass filter is a critical
element in determining important parameters as acquisition time, jitter, and stability.
Assuming proper design, the feedback mechanism converges and the DCO output
frequency reaches steady state, where
f ref
f DCO
p

 f DCO  f ref .
p
q
q
p
Since the ability of the loop to produce the desired frequency
f ref depends
q
primarily upon the nature of the DCO used, a decisive factor for the design of the loop is
the choice of the DCO. The choice of the DCO is crucial not only to generate an output
frequency which is, on the average, equal to the desired frequency, but also to keep the
jitter of the output signal within acceptable limits. The jitter of the DCO output is defined
as the maximum absolute deviation of a pulse edge of the DCO output from an ideal
p
waveform operating at the desired frequency f ref , assuming an initial synchronization.
q
From this definition of jitter its is clear that, for a frequency of the DCO output
p
slightly different from
f ref , the jitter will keep accumulating with time, ultimately
q
reaching 100 percent or, equivalently, one pulse discrepancy, unless the DCO output is
properly synchronized with the f q clock by periodically clearing the accumulator. In
addition to the fact that synchronizing the DCO by clearing the accumulator will bound
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the jitter, the overall operation of the DCO will become much simpler to analyze since a
predictable number of accumulations will occur during each cycle of the f q clock. This
will allow the frequency/phase of the DCO output signal to be compared with the
f q clock during each cycle of f q , and the result of the comparison to be available at the
input of the DCO at the very beginning of the next cycle, thus providing accurate
readjustments of the DCO.
b) Accumulator-Type DCO
K
fDCO=m.s.b
A
B
A+B
CLR
Sync
fs
LATCH
Figure 9: Accumulator-Type DCO
With the accumulator-type DCO, the DCO output is generated by successively adding
the value of an integer K to itself at the high frequency rate f s of a system clock. The
accumulator type DCO is made use of in this current design of ADPLL. The accumulator
type DCO along with the edge triggered JK flip-flop offer a powerful phase lock
mechanism. If t0 denotes the time when the latch is cleared by a sync pulse and if
1
Ts 
denotes the period of the system clock, the value at the output of the adder at
fs
time t n  t 0  nTs , that is, after the nth rising edge of f s , is
n
 k =nk modulo 2N. The
i 1
DCO output is given by the most significant bit of the output of the latch, so that the
DCO output frequency is given by the formula,
k
f DCO  N f s .
2
In effect, this latch acts as a phase register, which indicates the phase Φ(tn) of the
DCO output signal. As such, the above adder-latch arrangement constitutes a frequency
generator which operates at a fixed rate for given values of k and f s . In order to generate
the desired frequency
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p
f ref
q
this adder-latch arrangement is operated in conjunction with a frequency comparator
which searches for a value of k that leads to p pulses of the DCO output during two
successive rising edges of the f q clock. For given values of f q and f s , it is possible to
find at least one integer k which leads to less than (p+1/2) and more than (p-1/2) DCO
clock periods during a single cycle of the f q clock, if the number of bits of the
accumulator, N, satisfies the inequality
qf
N  log 2 s .
f ref
k
An N-bit accumulator can generate a frequency f DCO  N f s only if the system clock
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period Ts is longer than the critical data path delay,  (N ) , encountered throughout the
adder. The wider the adder, the longer the propagation delay, so that the delay  (N )
increases with the number of bits, N. As a result, the DCO can operate properly only
1
if f s 
. The N-bit output of the accumulator also provides the input to the error
 (N )
correction mechanism. This is inline with the predetermined jitter criterion. The chosen
jitter limit J is related to the number of bits n that need to be chosen among the total N
1
bits of the accumulator by J  n . The lower limit of the output signal can be given
2
according to this chosen jitter,
f DCO  Jf s
Therefore, the stronger the requirement on the jitter, the lower the maximum frequency
that can be generated with such an arrangement. Since it is necessary in practical
applications for the jitter of the generated signal to be much less than unity, the above
condition also implies that f DCO  f s . The lowest permissible constraint j min that can be
imposed on the jitter is,
f
1
.
j min  Ns1 .
f ref
2
q
1
The maximum tolerable jitter is only  50 0 0 corresponding to ( p  ) DCO
2
fs
output periods. This gives the upper bound on the output signal as, f DCO  N 1 .
j2
In summary, the DCO can generate signals over the dynamic range of
frequencies,
fs
 f DCO  jf s
j 2 N 1
f DCO 
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c) All Digital PLL with Accumulator-Type DCO
Figure 10: All Digital Phase Locked Loop using Accumulator DCO
In the current design the DCO performs the accumulation with every system
clock f s and it is reset at the falling edge of the reference signal. The accumulation is
done based on the incoming k value. This k value keeps changing every falling edge of
the reference signal. The m.s.b of the accumulated output gives the DCO output signal.
Based on this m.s.b a lead-lag signal is set and depending on the jitter condition a small
portion of the N bits (n) are taken out indicating the error or difference between the
reference signal and the generated signal. This is scaled and given to a successive
approximation block which modifies the value of k based on this value. The DCO
continues accumulation using this new value of k and this way the DCO output always
follows the reference signal.
IV. Design Process
The ISE CAD tool has been extensively used in the design of the All Digital PLL
(ADPLL). VHDL (VHSIC Hardware Description Language; VHSIC – Very High Speed
Integrated Circuit Design) is used to describe the hardware and XST (Xilinx Synthesis
Technology) synthesis engine is made use of. ModelSim Simulator is used to perform
behavioral, post-translate and post-layout simulations [6]. Hardware Description
Languages provide a lot of flexibility and advantages in the digital system design. The
capability to see the working of the system with out actually building the hardware
provides a lot of cost benefits. Changes can be made on the fly and one can keep updating
the design to meet the newly arising needs.
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The current design flow starts with the choice of the jitter requirement. Then
based on the incoming reference signal, system clock, the number of bits required for
internal computation is calculated. Based on this the ADPLL coding is done block by
block. The accumulator-type DCO, the successive approximation and the lead-lag blocks
are coded and integrated together using a schematic entry tool also provide by ISE CAD
tool. After successful coding the design is loaded onto a Xilinx FPGA. The post-layout
simulation can be seem using ModelSim simulator which provides the timing delays
encountered assuming that it has been placed onto the hardware. The area occupancy
onto the FPGA is measured in terms of its CLBs and IOBs that were dedicated for this
particular application [7], [8].
V. RESULTS
The ADPLL IP core has been implemented onto a Xilinx Virtex XCV50pq240
chip. The chip is having 57,906 system gates which are present among 384 CLBs
(configurable Logic Blocks). A maximum of 180 I/Os are present. The Virtex
XCV50pq240 is one of the primitive chips and after it several chips of grater densities
have been released. The current design of ADPLL IP Core occupies around a maximum
of 11% (which comes to around 45 CLBs) of the total chip space there by leaving a lot of
space for fitting the other components present in a bigger and complete SOC IC.
The IP core has been designed keeping in mind the portability, flexibility and optimality
criterion. The IP core can be used in any design suiting the given frequency
specifications. A system clock of 16 Mz is used. The IP Core is designed centering a
reference frequency of 400 Hz. It’s mainly meant for low frequency applications. It
provides a jitter of less than 0.1 degrees only. The current design with the 28 bit
accumulation used offers a frequency range of 300 Hz to 2 Mz. The design can be
extended beyond that also. But the logic criterion needs to be changed to overcome the
propagation delay that is introduced due to greater number of bits involved in the
computation.
f DCO
Sync
Figure 11: The f DCO following the reference signal.
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The synthesis and implementation reports have been given in the Appendix. They
give the exact count of the resources utilized by the current design. In addition to the
design entry, synthesis, simulation, implementation and final downloading on to the chip,
the ISE CAD tool provides a lot more features. The timing analysis tool can be used to
identify the exact times the signals are taking in the post-layout design. The area
constraints tool can be used to specify which portion of the chip the design should go into
by specifying the CLBs and the paths that the signals should be routed though. The
PACE (Pin out and Area Constraints Editor) utility lets the user to perform this very task.
The XPower utility lets to analyze the total power consumption. By setting the
appropriate routing path and utilizing these tools the design can be further optimized. The
change of platform also decides the power consumption. The latest Virtex Pro FPGAs
consume only 1.3 V power.
VI. REFERENCES
1. C. Rowen, “Reducing SoC Simulation and Development Time,” IEEE
Computer, vol.35, no.12, December 2002, pp.29-35.
2. Phase-Locked Loops: Design, Simulation & Applications By Roland E. Best, 4th
Edition, McGraw-Hill Professional Engineering.
3. Using FPGAs for DPLL Applications, Actel Programmable Logic Solutions
http://www.actel.com/documents/s04_18.pdf.
4. Phase Locked Loops: A control Centric Tutorial by Danny Abramovitch.
www.web-ee.com/primers/files/pll_tut_talk.pdf.
5. S. Walters and T. Troudet, “Digital Phase-Locked Loop with Jitter Bounded”,
IEEE Transactions on Circuits and Systems, Vol. 36, No. 7, July 1989.
6. VHDL: Programming By Example by Douglas L. Perry - McGraw-Hill
Professional, 2002.
7. Xilinx Spartan II FPGA Complete Data Sheet. http://direct.xilinx.com/
bvdocs/publications/ds001.pdf.
8. Xilinx Software Manuals and Help for Xilinx ISE CAD Tools
http://www.xilinx.com/support/sw_manuals/xilinx5/index.htm.
9. Digital Signal Processing with Field Programmable Gate Arrays by Uwe MeyerBaese, Springer-Verlag publishers.
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