1
A Fast-Locked All-Digital Phased-Locked Loop
Using Successive-Approximation
Frequency-Search Algorithm
Dian Huang and Ying Qiao

Abstract— All-Digital Phase-Locked Loop (PLL) for digital
system clock generation is widely studied to replace the traditional
analog PLL as the CMOS process technology enters the
nanometer regime. Numerous researches have been performed to
reduce the frequency and phase locking time as well as mitigating
the output clock jitter. This paper discusses popular ADPLL
controller algorithms as well as their hardware realizations and
evaluates their effectiveness. However, because of the complex
trade-off relationship between locking time and clock jitter, a
novel scheme free of this conflict is proposed by using the
successive-approximation frequency-search algorithm.
Index Terms—all digital phased-locked loop (ADPLL),
bang-bang phase frequency detector (BBPFD), successive
approximation algorithm (SAR)
I. INTRODUCTION
A
digital system such as system-on-chip microprocessor
generally requires Phased-Locked Loop (PLL) for clock
generation. However, traditional analog PLL typically contains
several important components not included in a standard cell
library, such as resistor and low leakage capacitor, which
makes it difficult to integrate into a digital system. In addition,
its performance is limited by process, voltage, and temperature
variation.
In recent years, the benefits from technology scaling have
enabled the implementation of all-digital phase-locked loop
(ADPLL). Many different approaches on ADPLL have been
proposed for clock generation. In [1], high-resolution
time-to-digital converters (TDC) have been integrated in
ADPLL to replace the analog charge pump; however, the
resolution is limited by the delay of single inverter. Although
Vernier delay line [2] time-to-digital converter has been
proposed and the resolution is reduced to around several
picoseconds, such design is challenged by its complexity and
power consumption.
In order to alleviate the resolution requirement of
conventional TDC-based ADPLL, bang-bang ADPLLs have
become popular. However, such architecture suffers from long
settling time and may cause stability problem if the output
Dian Huang and Ying Qiao are with Department of Electrical Engineering and
Computer Sciences, University of California, Berkeley
E-mail: (dianhuangmarch05, yingqiao) @ berkeley.edu.
frequency is far from the center frequency [3]. Thus, several
techniques have been proposed to reduce the locking time of
bang-bang ADPLL. In [4] and [5], the bandwidth of the system
is adaptively self-adjusted. A large proportional gain is used
initially to settle the phase and frequency error to a smaller
value and then a small gain is used for fine resolution.
Thus, in this work, we proposes a novel successive
approximation frequency-search algorithm to not only center
the starting frequency of digitally controlled oscillator (DCO)
on the desired frequency but also align the phase of the output
clock to that of the reference clock. In this algorithm, the
settling mainly depends on the DCO control bits instead of the
bandwidth of the system. Therefore, fast-lock can be achieved
despite of a low bandwidth system.
This paper is organized as below. In section II, we will
discuss the design considerations and major challenges of the
fast-locking ADPLL. Several examples of fast-locking ADPLL
algorithms and hardware implementation are discussed in
Section III. Our proposal for SAR-based ADPLL is shown in
Section IV with conclusions in Section V.
Figure 1 Conventional ADPLL Architecture
II. ADPLL DESIGN CONSIDERATIONS
In history, high-resolution time-to-digital converters (TDC)
have been integrated in ADPLL to replace the charge pump
used in analog PLL. Various types of TDC have been proposed
to imitate the behavior of a charge-pump. In this type of PLL,
the locking behavior is similar to that of analog, but its
complexity and resolution limits its jitter performance.
Therefore, nonlinear BBPD becomes popular. However, a
conventional bang-bang ADPLL generally has to adjust the
output frequency and phase through the binary UP/DN
bang-bang code, which makes it suffer from long settling time
2
and may cause stability problem if the output frequency is far
from the center reference frequency.
The settling time of conventional bang-bang ADPLL
generally strongly relies on the bandwidth of system because
the gain of the system determines how much phase error a PLL
can correct for each cycle. In [3], this relationship is analyzed.
For a first order system, the lock time can be expressed as:
𝐭 𝒍𝒐𝒄𝒌 =
𝝅
𝟏
𝟐𝝅
×(𝜷𝒌𝒗𝒄𝒐 −𝒇𝒐𝒇𝒇 ) 𝒇𝒓𝒆𝒇
𝒇𝒓𝒆𝒇
1
(
)
whereas fref is the reference clock frequency, 𝛽 is the
proportional gain, and foff is the initial frequency error.
When 𝛽𝑘𝑣𝑐𝑜 , the gain of the system, is smaller than initial
frequency error, the system becomes instable and can never
settle.
With this introduced bounding for the proportional gain on
first-order bang-bang ADPLL, a large gain is needed to prevent
instability problem. However, for a first order system, a large
beta value directly affects the frequency step of the DCO,
which is proportional to the jitter performance. Thus, an
integral path is implemented to find the desired output
frequency of the DCO and prevent instability problem.
However, this integral path also contributes to the output jitter.
As shown in [6], the peak-to-peak output jitter is related to both
integral path gain and proportional path:
t 𝑝𝑝 =
𝑁𝑘𝑣𝑐𝑜
4𝑞 2
((1 + 𝐷)4 𝛼 3 + 4(1 + 𝐷)3 𝛼 2 𝑞 + 8(1 + 𝐷)2 𝛼𝑞2 +
8(1 + 𝐷)𝑞3 )
(2)
𝐪 = 𝛃−
𝛂(𝟏+𝟐𝐃)
𝟐
(3)
where N is the divide ratio, D is the delay cycle of loop gain, 𝛼
is the integral path gain. As shown in Figure 2, the output jitter is
directly related to the q value above.
we will briefly review several fast-locking ADPLL
architectures recently proposed in literatures. We then
summarize and compare their circuit performances of chips
implemented on sub-micro CMOS technologies in the
following section.
A. Locking both Frequency and Phase At the Same Time
1) Modified Bang-Bang Algorithm: During the settling
period, PLL generally reaches the desired frequency in a much
shorter time than phase-locked. Due to a huge phase error, it
still needs to adjust its frequency away from the desired in order
to cancel out the phase error. This dramatically increases the
settling time. Therefore, a modified bang-bang algorithm [7]
has been proposed to resolve the above issue. In phase
adjustment period, the proportional path changes the frequency
hugely for phase alignment; however, as long as the bang-bang
phase detector outputs a lead followed by a lag or vice-versa,
the phase adjustment is ended, and the PLL goes back to
frequency adjustment period to correct the frequency error due
to phase adjustment. Thus, in this algorithm, it keeps track of
the proportional path code, which generally changes the
frequency hugely due to a large beta value, and clears all the
proportional path code so that the frequency changes back to
the original one, as shown in figure 3. At time t1, despite that
the DCO output frequency has been close to the desired output
frequency, it still increases to adjust its phase error. However,
the phase error is adjusted, it clear the proportional code and
leaves the integral path code, which results in huge frequency
drop back to the a point close to the final DCO output frequency
because the integral path code is generally small and able to
detect the right frequency due to its summation over all
previous phase polarity code. When the phase error is small
enough, this algorithm is disabled and the PLL works as same
as the conventional one.
This algorithm does improve the settling time, as indicated in
figure 4; however, it still suffers from two issues: first, this
works only for when the DCO frequency is close to the desired
frequency; second, the how fast the PLL can reach phase
adjustment period still depends on the bandwidth of the system,
and thus, the trade-off between jitter and settling still applies.
Figure 2 Relationship of output jitter Δtpp and path gains
Figure 3 Code of the DLF with the modified bang-bang algorithm.
III. ADPLL FAST-LOCKING TECHNIQUES
As a result, many fast-locked ADPLL architectures have
been proposed to alleviate the above tradeoff. In this section,
3
(a)
(b)
Figure 4 Simulated transient responses for
(a) ADPLL with a BBPD and a fixed proportional gain and (b) ADPLL
using the modified bang-bang algorithm
2) Adaptive Loop Gain Algorithm: Since a fixed bandwidth
generally has the trade-off discussed, an adaptive-loop gain
fast-locked algorithm is proposed in [4]. Although cycle
slipping generally occur when the frequency error is large, the
average phase error can still be used to predict the correct
frequency because the BBPFD will make constant up or down
signals during the frequency tracking. In this algorithm, the
average value of these signals are transformed through leaky
integrators, which form an IIR filter that dynamically changes
the loop gain of the system depended on the average phase
error. Thus, when the frequency error is large, the gain is also
large for shorter lock time. When the error is small, it changes
the loop gain to a very small one for low jitter performance.
However, this algorithm suffers from several issues. First, an
extra IIR filter in the loop increases the hardware complexity,
since full adders are generally required. Second, in order to
adaptively change the gain of a system, the actual DCO gain
needs to be estimated properly during simulation in order to set
the coefficient of the IIR filter correctly; however, due to
process and temperature variation, the optimal coefficient
generally also needs to be changed. In order to resolve the issue
of process and temperature variation, dynamically reconfigured
digital loop filter is proposed in [4]; although it is able to adjust
the gain corresponded to the current environment; it
significantly increases the hardware complexity.
B. Detangle the locking of Frequency and Phase
Since one of the major problems during PLL settling is that
correcting the phase error always need to change an already
close output frequency, the proposed ADPLL in [9] separates
the scheme for the frequency acquisition and phase locking,
i.e., it aligns the clock frequency first through search algorithms
and locks the phase later by TDC-based techniques.
1) Binary Frequency Search: In frequency-tracking phase,
the BBPHD detects the phase error between the reference clock
and the divider output clock. It outputs an up or down signal to
increase or decrease the output frequency of DCO accordingly.
When the BBPHD outputs an up signal followed a down in the
previous clock cycle or vice-versa, the frequency settles within
the range of current step size of the DCO control code. In this
situation, the control code switches to next significant bit,
reducing the step size.
The BSA is implemented easily and can achieve a fast
locking. The maximum locking time is proportional to
O(log2N) , where N is the number of discrete frequency point in
the DCO. Thereby, a tradeoff among locking time, frequency
range, and DCO gain must be made when the BSA is utilized in
an ADPLL.
2) TDC Fast-Phase Tracking: Despite that the frequency
settles down to the desire frequency, the phase is still not
aligned. As a result, during the phase-tracking phase, it adapts
back to TDC technique for fast-phase track. With the previous
frequency-search algorithm, the frequency already settles, and
thus, the remained phase error can be eliminated by adjusting
the period of several DCO output clocks to align the phase, and
then its frequency changes back to the original settled one.
Therefore, the TDC senses the phase error P, and generates the
output code Q. In [9], for N cycles of the DCO output, Q/2 of
them have a period of Toriginal + ΔDCO. Therefore, during these N
cycles, N-Q/2 have the original period, and Q/2 has the new
period. This reduces the phase error by ΔDCO*Q/2.
This fast-phase tracking techniques significantly improve the
phase alignment time because the actual frequency of the DCO
clock is, in fact, not affected by the phase-tracking process, but
the main issue is the need of a ultra-high speed counter with
operating frequency as same as the output clock. Still, although
TDC can generate the digital code corresponding to the amount
of phase error, it suffers from limited resolution and large area.
Figure 5 Fast phase tracking with the TDC and the DSM
IV. COMPARISON
As explained in section III, many researches have been
4
conducted in real environment. Table 1 summarizes process
technology, locking time, jitter RMS, core area and power
consumption of recently reported ADPLL designs. These data
will be good references for comparison of different algorithms
implemented in the ADPLL core for fast-locking clock
generation applications.
is greatly reduced compared to all algorithms discussed in the
previous section. It generally needs several N-bit shift registers
to implement the SAR frequency-search for an N-bit DCO.
Reset
DCO
Set DCO[MSB]=1
V. PROPOSED WORK
The ADPLLs implemented with frequency-search and
phase-locking algorithms in the previous section have their
common tradeoffs. The major issue is that when the ADPLL is
adjusting the frequency discrepancy, it may not be reducing its
phase error; meanwhile, it is not able to reduce its phase error
without changing the original frequency. With this inherent
conflict, the frequency settling and phase locking time strongly
depend on the bandwidth of the system loop gain.
Therefore, this work proposes a novel successive
approximation (SAR) frequency-search algorithm to not only
center the starting frequency of DCO on the desired frequency
but also align the phase of the output clock to that of the
reference clock.
For the first cycle, the MSB of the DCO is set to 1, and the
ADPLL resets its DCO until the falling edge of the reference
clock, as shown in Figure 6. Due to a fast startup of the ring
oscillator, the phase of the feedback clock from the output of
the divider is automatically aligned with the reference clock.
On rising edge of the reference clock, the BBPD produces an up
or down signal to indicate whether the DCO frequency should
be faster or slower, which determines whether the MSB of
DCO should be 1 or 0. For the next several cycles, the other
control bits are determined similarly. Once the frequency
search is done, not only the DCO outputs the desired frequency
but also the phase is locked. Finally, under this locked
condition, the ADPLL operates the same way as those
conventional ones. The circuit implementation of this proposed
scheme will employ mature blocks, such as BBPD, DCO and
dividers. Our design focus will be on the ADPLL controller
FSM, which controls the DCO control code generation.
There are several major advantages with the proposed
approach. First, the locking time no longer depends on the
bandwidth of the system, which makes an ADPLL with narrow
bandwidth and low jitter possible. Second, the frequency range
of the DCO can be significantly large because the locking time
is only O(log2N) reference cycles, whereas N is the control code
length. Third, the hardware complexity of this type of algorithm
1->MSB
Tref_clk<Tdiv?
0->MSB
Set DCO[MSB-1]=1
1->[MSB-1]
Tref_clk<Tdiv?
0->[MSB-1]
1->[LSB]
Tref_clk<Tdiv?
0->[LSB]
Done = 1
(a)
delay cell
done
INV
ref_clk
DCO output
(b)
Figure 6 Flowchart of proposed SAR algorithm (a)
with modified binary DCO (b)
VI. CONCLUSION
This paper discusses several different types of fast-locking
ADPLL recently published and compares their chip
performances from measurement data. We analyzes the
strengths and weakness of these techniques and propose our
successive- approximation algorithm to improve the frequency
and phase locking time without much scarification of output
clock jitter. Further work will be on the realization of this
ADPLL control scheme.
Table 1 Performance Comparisons of Various ADPLL Implementations
Parameter
[9] Chung
Error! Reference
source not
found. Hsu
CMOS Process
Area
Power
Output Range
Locking Time
65nm
0.07mm2
0.18µm
0.14 mm2
90nm
NA
90nm
0.3 mm2
0.13µm
0.2 mm2
1.81mW@520MHz
26.7mW@600MHz
7.1mW@10GHz
46mW@40GHz
16.5mW@1.35GHz
90~527MHz
NA
62~616MHz
NA
9.75~10.17GHz
6.9µs
37~40GHz
15µs / 50MHz
0.3~1.4GHz
NA
[4] Yang
[7]Hung
[8] Kim
5
Jitter RMS
Jitter peak-to-peak
8.64ps @527MHz
NA
7.28ps @600MHz
56ps @600MHz
NA
NA
[5]
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[1]
[2]
[3]
[4]
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[7]
[8]
[9]
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NA
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