603410014 蔡宜哲
603410065 楊佳榮
Introduction:
An all digital phase-locked loop (ADPLL) is a system that generates an output
signal whose phase angle is equal to a reference signal. The basic blocks of the
ADPLL are Frequency Detector (FD), Phase Detector (PD), PLL Controller, Digital
Controlled Oscillator, Frequency Divider. It is widely used in telecommunications,
electronic application, radio, etc.
Past work:
The frequency detector is a device that compares the frequency of two input
signals. The two input signals correspond to the output of digital controlled oscillator.
It has two outputs signals which show how to adjust the DCO frequency. The phase
detector is an essential element in ADPLL. It generates a signal which represents the
phase error between two input signals. The PLL Controller is an element that receives
the output signals from PD and FD which generates DCO code to the digital
controlled oscillator. The digital controlled oscillator produces an oscillating signal
after receiving the DCO code from controller. The frequency of DCO is depended on
the DCO code, the more DCO code it is, the more frequency signal it is. The
frequency divider is a circuit that reduces the frequency of DCO output signal. The
PD or FD could not work if the input signal is in high frequency.
Present work:
I am concentrating on making all the sub-circuit and combining into
ADPLL .With previous practices, I have learned a wide range of knowledge about
digital circuit design and phase-locked loop which would make me easy to deal with
the complicated circuit design.
For FD and PD, I design two D-flip flops to detect whether the reference clock
leads feedback clock or not. Besides, a series of buffers are needed to amplify the
phase error to be large enough to defeat the filter. As for DCO, I take a parallel
structure to control the strength of input signal. It has two benefits. One is that we can
easily adjust the control code by simply modifying input vector. The other is that the
design is based on standard cells which means we do not have to create a unique
layout by ourselves. It saves lots of time and money due to the design strategy. The
last circuit is frequency divider. It is necessary because the transfer rates of input and
output pad are not as fast as output frequency which would result in wrong message if
we do not take any action. The purpose of frequency divider is to divide the output
clock into slower frequency as to keep the rate of reference clock and output clock
equivalent.
As far, I have already designed frequency detector, phase detector, digital
controlled oscillator and phase-lock loop which are edited in Verilog. There are still
several issues needed to take into consideration even though most of circuits are
finished. Based on the reference clock, I can easily observe frequency and phase error.
Unfortunately, the reference clock is not continuously pure which makes an extremely
short spur in the spectrum sometimes. The spur would destroy the phase-locked state
and force the digital control oscillator to change control code, so it will take extra time
to keep the balance between reference clock and feedback clock. In other words, the
performance of phase noise is unsatisfactory. The other significant issue is power
consumption. In time to digital converter and phase detector, they consist of a number
of D-flip flops which are made of many transistors that would cost gigantic power.
future work:
I will improve the time to digital converter by replacing D-flip flop into other
component to reduce high power consumption. In addition, designing extra digital
loop filter to release the spur caused by jitter is a brilliant solution. After overcoming
above difficulties, I will merge total sub-circuit into all digital phase lock loop. Later,
I will run the simulation to test whether the behavior of the ADPLL is correct or not
and the synthesis to test whether the circuit is able to be manufactured or not. As long
as above check is perfect, I will execute the software called Encounter which will
generate a series of information and do a detail specification. If there is no error, the
layout will be sent to CIC and made into a chip.
Conclusion:
ADPLL is generally used in wireless communication network. Instead of analog
control, we adopt digital control for sake of precise measurement. Moreover,
ADPLL with frequency divider is adaptable for any frequency of reference clock
which can apply in most of modern network communication such as smartphone.
Small size and lower cost is another advantage which is attractive to company to
create. I hope this design would popularize and be widely used one day.