7.1 Objectives
Introduction to Decoders, Multiplexers, Decoder/Demultiplexer, and
Decoder/Drivers .
7.2 Background
7.2.1 Magnitude Comparator
A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes. The output of the comparison is specified by three binary variables that indicate whether A > B,
A = B, or A < B.
Block diagram of the magnitude comparator
If A and B are n-bit numbers, then a single combinational circuit module has
2
2n rows in its truth table, and becomes too cumbersome even with n=3.
We shall investigate the regularity possessed by the comparator circuit, and seek to reduce the design effort. A regular circuit usually can be described (designed) by way of an algorithm.
Let n = 4, i.e., A = a
3 a
2 a
1 a
0
, and B = b
3 b
2 b
1 b
0
. Define the equality indicator
x i
 a i

b i
= a i b i
+ a i
’b i
’ , 0 ≤ i ≤ 3
F
1
= (A = B) = x
3 x
2 x
1 x
0
F
2
= (A
>
B) = (a
3
> b
3
)
+ (a
3
= b
3
) · (a
2
> b
2
)
+ (a
3
= b
3
) · (a
+ (a
3
= b
3
) · (a
2
2
= b
2
) · (a
= b
2
) · (a
1
1
> b
1
)
= b
1
) · (a
0
> b
0
)
= a
3 b’
3
+ x
3 a
2 b’
2
+ x
3 x
2 a
1 b’
1
+ x
3 x
2 x
1 a
0 b’
0
F
3
= (A
<
B) = a’
3 b
3
+ x
3 a’
2 b
2
+ x
3 x
2 a’
1 b
1
+ x
3
x
2 x
1 a’
0 b
0
= (F
1
+ F
2
)’
7.2.2 Decoders
A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n
unique output lines.
It can be implemented with
AND gates.

If the n-input decoded information has unused or don't care combination, the decoder output will have fewer than outputs.
The decoders presented here are called n-to-m-line decoders, where m≤2 n .
Figure 4.1 shows a 3-to-8 decoder.
The decoder output variables are mutually exclusive because only one output can be equal to 1 at any time. The output line whose value is 1 represents the minterm equivalent of the binary number presently available in the input lines (see figure 4.2).
Inputs Outputs
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
Most, if not all, IC decoders include one or more enable inputs to control the circuit operation. Figure 4.3 shows a 1-to-2 decoder with enable.

Larger decoders can be implemented using smaller decoders, for example two-tofour decoder with its enable inputs can be used to build a three-to-eight decoder as shown in figure 4.4.
A decoder can provide all 2 n
minterms of n input variables. Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n
decoder in conjunction with m external OR gates. The Boolean functions for the circuit should be expressed in sum of minterms.
Example 4.1:-
Implement the binary adder {S,C} = X+Y+Z (where + is the arithmetic addition) using a decoder and OR gates.
S(X,Y,Z) = Σ(1,2,4,7); C(X,Y,Z) = Σ(3,5,6,7)

Solution:-
Figure 4.5 shows the answer:
7.2.3 Encoders
The terms encoder, decoder and code converter are often used interchangeably.
Encoders and decoders are widely used in communications. An encoder basically converts its input into an output code with a fewer number of lines. A decoder is later used to re-construct the original representation of the data again (see figure 4.6).
An encoder is a combinational circuit that performs the inverse operation of a decoder. It can be implemented with OR gates. An encoder is a circuit whose output code has normally fewer bits than its input code. The simplest encoder to build is a 2 n
-to-n or binary encoder. It has the opposite function as a binary encoder. Figure 4.7 shows an 8-to-3 encoder.
Equations for an 8-to-3 encoder:
Y0 = I1 + I3 + I5 + I7
Y1 = I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 + I7

7.2.4 BCD-to-Seven-Segment Decoder
The BCD-to-seven-segment decoder produces the seven outputs (a; b; c; d; e; f; g) from the 4-bit BCD input (see figure 4.8).
The logic-0 denotes that the corresponding segment is turned off, while logic-1 denotes a turned-on segment. The don’t-care conditions help minimizing the logic circuit, but they also produce meaningless displays for the unused input combinations, so they are all assigned 0 here. The number of gates can be reduced by sharing the common terms.
7.2.5 Multiplexer
A multiplexer (MUX) is a combinational circuit that selects (usually by n select lines) binary information from one of many (usually 2 n
) input lines and directs it to a single output line. Also it called a selector. Figure 4.9 shows a 4-to-1 multiplexer.

A multiplexer bears no resemblance to a decoder. On the contrary, it can be viewed as extended from a decoder (see figure 4.10).
Two or more multiplexers may be enclosed within one IC package, sharing selection and enable inputs.
MUX = decoder + OR gate + selectable/controllable minterms.
An n-variable Boolean function can be implemented with a 2 n -to-1 or 2 n-1 -to-1
MUX (see figure 4.11): if m i
is to be included in f, set I i
=1, else set I i
=0.

Combinational circuits can be implemented using multiplexer alone, or with minimal glue logic as illustrated in the following figure.
7.2.6 Demultiplexers
The demultiplexer (DMUX or DEMUX) performs the inverse function of a multiplexer, that is it receives information on one line and transmits its onto one of 2 n
possible output lines. The selection is by n input select lines.
Note that a one-to-four multiplexer is really a two-to-four decoder with an additional enable (E) input which is the input data line.

7.3 Preliminary Work
Derive the truth table and draw a schematic diagram for each experimental part.
7.4 Lab Work
174LS151 8-channel multiplexer.
274LS85 4-bit magnitude comparator.
374LS138 3x8 decoder.
474LS47 decoder/driver.
57-Segment display.
The 7485 is a device that has the capability to perform a logical comparison of two 4-bit binary numbers. a) Connect A n
and B n
inputs of the 7485 to switches and outputs to LEDs and connect the enable inputs according to the truth table. Note that if there is not enough switches use Vcc for 1 condition and GND for 0 conditions.
Show in schematic diagram the circuit connection. b) Verify the operation of the comparator using the truth table given in the data sheet. c) Simulate your results using PROTEUS.
The 74LS151 is a device which routes one of eight input line to a single output line.

a) Any single input may be obtained at the out put by properly selecting S
0
,
S
1
and S
2
input .connect those three inputs to switches, And connect all data inputs to switches. Show in a schematic diagram the circuit connection. b) Verify the operation of the 74151 multiplexer using the truth table given in data sheet. c) Simulate your results using PROTEUS.
The 74LS138 is a 1 of 8 decoder or 3 lines to 8 line decoder. The reason for this is that it selects one of eight outputs when proper binary code is represented at its three inputs (selection lines). a) Connect inputs A
0
, A
1
, and A
2
switches, the enable inputs to switches, and all data outputs to LEDs. Show in a schematic diagram the circuit connection. b) Verify the operation of the 74138 decoder using the truth table given in data sheet. c) Simulate your results using PROTEUS.

The 7447 is a sophisticated 4 lines to 7 lines decoder used mainly to derive a common anode (CA) 7 segment displays.


A seven display is a device which digital systems uses to display decimal numbers from 0 - 9. A 7-segment display contains seven separate LEDs and 1 or 2 decimal points. These LED segments are labeled individually by the letters a,b,c,d,e,f,g. a) Connect inputs A, B, C, and D to switches and the 7 segment display to the outputs of the 7447. b) Momentarily close the lamp test switch (after connecting the 7 segment display) and all segments should be “ON” As the name implies, this is a test to verify that all segments are connected to the IC. However This does not imply that the connections are right!!. Open the lamp test switch. c) Using the truth table of the 7447 from the data sheet, verify that the proper segments are ON corresponding to the given BCD code input. d) The 7 segment display has a left decimal point, connect this input to a switch and verify that it is turned ON, OFF accordingly. e) Show in a schematic diagram the circuit connection. f) Simulate your results using PROTEUS.
7.5 Report Exercises
1.
Design a 4-line to 16-line decoder using two ICs 138. (show schematic diagram).
2.
Show in a schematic diagram how a decoder like 74138 can be used as a demultiplexer. (show necessary connections).
3.
Use two ICs 7485 to compare the magnitude of two 8-bit binary numbers.
(show schematic diagram).