Highly Impermeable Graphene Nanosheet for Next-Generation
Barrier of Cu Interconnect
Yuda Zhao and Yang Chai*
Department of Applied Physics, The Hong Kong Polytechnic University, Hong Kong, China.
*E-mail: ychai@polyu.edu.hk
In the state-of-the-art Cu/low-k interconnect technology, a thin barrier is used between
the Cu conductor and the surrounding dielectrics to prevent Cu from diffusing into dielectrics.
According to the International Technology Roadmap for Semiconductors in 2011, the
thickness of the barrier layer for the Cu interconnect is projected to be less than 1 nm by 2021.
It has been expected that the current Cu barrier material may fail at such a small dimension.
To enable the continuous downward scaling of the Cu interconnect, it requires the researchers
to develop the ultra-thin layer (<2 nm) with high resistance to Cu diffusion.
Graphene has ultra-thin thickness (<1 nm), single-crystal hexagonal structure, high
impermeability,1-4 excellent electrical conductivity and high thermal stability. These properties
make graphene-based materials promising for the barrier of the Cu interconnect. Our desnity
function theory calculation suggests that Cu species can penetrate graphene nanosheets
through defects that are larger than 0.25 nm2. The intrinsic defects in as-grown graphene can
be avoided by layer-by-layer graphene transfer process. As a result the thickness of graphene
barrier for completely blocking Cu migration can be 5 times smaller than that of conventional
TaN barrier4. The graphene barrier also inhibits electrochemical reactions and reduces Cu ion
density at the interface between Cu and SiO2.
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