EE 458
LAB REPORT
EXPERIMENT 3
PHASE LOCKED LOOPS
Purpose:
The objectives of this laboratory are:
1. To introduce students to Phase Locked Loops (PLL) and their operation.
2. To predict and measure the PLL characteristics.
3. To set up practical circuits using the PLL.
Equipment List
1. PC with Matlab and Simulink
The Phase Locked Loop Principle:
The phase locked loop is a feedback system comprised of a phase comparator, a low pass
filter and error amplifier in the forward signal path and a voltage-controlled oscillator (VC0) in
the feedback path. The block diagram of a basic PLL system is shown. Perhaps the single most
important point to realize when designing with the PLL is that it is a feedback system and, hence,
is characterized mathematically by the same questions that apply to other, more conventional
feedback systems. The parameters in the equations are somewhat different, however since the
feedback error signal in the phase locked system is related to phase rather than to current or
voltage, as is usually the case in conventional feedback systems.
LOOP OPERATIONS:
Figure 3 A (a) PLL operation
From a qualitative point of view, the basic principle of PLL operation can be briefly
explained. With no signal input applied to the system, the error voltage Ve is equal to 0. The
VCO operates at a set frequency wo, which is known as the free-running frequency. If an input
signal is applied to the system, the phase comparator compares the phase and frequency of the
input signal with the VCO frequency and generates an error voltage Ve(t) that is related to the
phase and the frequency difference between the two signals. This error voltage is then filtered,
amplified and applied to the control terminal of the VCO. In this manner, the control voltage vd(t)
forces the VCO frequency to vary in a direction that reduces the frequency difference between fo
and the input signal. If the input frequency wi is sufficiently close to wo, the feedback nature of
the PLL causes the VCO to synchronize or lock with the incoming signal. Once in lock, the VCO
frequency is identical to the input signal except that for a finite phase difference.
Figure 3 A (b) Input power spectrum
This net phase difference is  is necessary to generate the corrective error voltage Vd to shift the
VCO frequency from its free-running value to the input signal frequency wi and thus, keep the
PLL in lock. This self-correcting ability of the system also allows the PLL to track the frequency.
Figure 3 A (c) Block parameters of input power spectrum
The range of frequencies over which the PLL can maintain lock with an input signal is defined as
the “lock range” of the system. The band of frequencies over which the PLL can acquire lock
with an incoming signal is called “Capture range” of the system and is never greater than the
“lock range”. Another means for describing the operation of the PLL is to observe that the phase
detector is in actuality a multiplier circuit that mixes the input signal with the VCO signal. This
mix produces sum and difference frequencies wi +- w0. When the loop is in lock, the VCO
duplicates the input frequency so that the difference frequency wi – wo is zero, hence the output
of the phase comparator contains a dc component. The low pass filter removes the sum frequency
component wi + wo but passes the dc component, which is then amplified and fed back to the
VCO. Notice that when the loop is in lock, the difference frequency component is always dc, so
the lock range is independent of the band edge of the low pass filter.
Figure 3 A (d) Block parameters of Analog filter design
LOCK AND CAPTURE:
Figure 3 A (e) Input scope
Consider now the case where the loop is not yet in lock. The phase comparator again mixes the
input and VCO signals to produce sum and difference frequency components. If the difference
frequency is above the cut off frequency of the low pass filter, no signal is transmitted around the
loop and the VCO remains at its initial free-running frequency. As the input frequency
approaches that of the VCO, the frequency of the difference component decreases and approaches
the band edge of the low pass filter. Now some of the difference component is passed, which
tends to drice the VCO towards the frequency of the input signal. This, in turn decreases the
frequency of the difference component and allows more information to be transmitted through the
low pass filter to the VCO. This is essentially a positive feedback mechanism, which causes the
VCO to snap into lock with the input signal. With this mechanism in mind, the term, “Capture
range” can again be defined as the frequency range centered about the VCO initial free-running
frequency over which the loop can acquire lock with the input signal. The capture range is a
measure of how close the input signal’s frequency must be to that of the VCO to acquire lock.
The “capture range” can assume any value within the lock range and depends primarily upon the
band edge of the low pass filter together with the closed loop gain of the system. It is this signalcapturing phenomenon which gives the loop its frequency selective properties.
Figure 3 A (f) Block parameters of VCO
Figure 3 A (g) Block parameters of error rate calculator
Figure 3 A (h) Output power spectrum
It is important to distinguish the “capture range” from the “lock range” which can, again be
defined as the frequency range usually centered about the VCO initial free-running frequency
over which the loop can track the input signal once lock has been achieved.
When the loop is in lock, the difference frequency component on the output of the phase
comparator (error voltage) is dc and will always be passes by the low pass filter. Thus, the lock
range is limited by the range of the error voltage that can be generated (Vd) and the
corresponding VCO frequency deviation delta wo produced. The lock range is essentially a dc
parameter and is not affected by the band edge of the low pass filter.
Frequency Tracking:
Figure shows the typical frequency-to-voltage transfer characteristics of the PLL. The
input is assumed to be a sine wave whose frequency is swept slowly over a broad frequency
range. The vertical scale is the corresponding loop error voltage. The top figure shows the input
frequency being gradually increased. The loop doesn’t respond to the signal until it a frequency
w1, corresponding to the lower edge of the capture range. Then, the loop suddenly licks on the
input and causes a negative jump of the loop error voltage. Next Vd varies with frequency with a
slope equal to the reciprocal of VCO gain (1/ Ko) and goes through zero as wi = wo. The loop
tracks the input until the input frequency reaches w2, corresponding to the upper edge of the lock
renge. The PLL then loses lock and the erro voltage drops to zero. If the input frequency is swept
slowly back now, the cycle repeats itself, but it is inverted, as shown in the lower fig. The loop
recaptures the signal at w3 and tracks it down to w4. The total capture and lock ranges of the
system are:
2wc = w3 – w1 and 2wL = w2 – w4
Note that the PLL system has an inherent selectivity about the center frequency set by the VCO
free-running frequency wo. It will respond only to the input signal frequencies that are separated
from w0 by less than wL or Wc, depending on whether the loop starts with or without an initial
lock condition. The linearity of the frequency-to-voltage conversion characteristics for the PLL is
determined solely by the VCO conversion gain. Therefore, in most PLL application, the VCIO is
required to have highly linear voltage-to-frequency characteristics.
Measuring Constants
We started our experiment on PLLs by first measuring the different parameters of each
functional block.
1. Multiplier Constant, Km
With a 1V p-p sinusoidal voltage at both inputs of the multiplier, the output was observed and
the multiplier constant was calculated to be 0.206.
2. Phase Detector Constant, Kd
The phase detector consists of an analog multiplier and a limiter to remove the amplitude
variations in the input signal.
Kd = peak output voltage of the limiter * peak voltage of the VCO * multiplier constant
Kd = (1.86 x 2) x (2.199 x 2) x 0.206
Kd = 1.72 volts
3. VCO Conversion Constant, Ko
An external voltage may control the output frequency of the VCO. The change in the output
frequency per change in the dc input voltage was measured.
Ko = f / v
Ko = 1 / 0.5 = 2 kHz/sec/volt
Ko = 4103 = 12566 rad/sec/volt
4. Total Loop Gain, KT
K T = K d x K o.
= 1.72 x 12566 = 21613.52
5. Low Pass Filter
Two first-order low pass filters are used. The cutoff frequencies for one of the low pass filters
is 100Hz and the other is 1kHz. This was verified by using the white noise as the signal
source and then checking the filter output spectrum on the spectrum analyzer. The power
spectral density for the white noise is uniform at input – i.e., power of equal amplitude exists
approximately at all frequencies. In the output spectrum, the roll off occurred at
approximately 100 Hz and 1kHz respectively.
The spectrum analyzer was configured to act as the source of random white noise. To obtain
the maximum noise output, the attenuation level was set to 0 dB. This was fed to the low pass
filters and the output was observed on the spectrum analyzer.
The same procedure was repeated for the 4th order low pass filter. In this case, the filter knob
was adjusted so that the 3 dB roll off occurred approximately at 2 kHz.
Phase Lock Loop Operation
The circuit is connected as shown in the schematic. The open loop system is closed and using
a jumper around it by-passes the filter. The capture and the lock ranges for the PLL are
calculated. By varying the Philips frequency, and using a frequency counter along with the
DC voltmeter, the capture and the lock ranges are measured. The signals within the PLL are
observed on the oscilloscope.
The above steps are repeated using the 1kHz cut off low pass filter and then the 100 Hz cut
off low pass filter.
Calculations:
The values of Lock and Capture Range obtained by calculations were:
Lock Range:
2L = 2KT
2fL = KT /  = 6880 Hz.
Capture Range:
2fC = 2 fL * f3
Using a 100 Hz cutoff 1st order low pass filter, f3 = 100Hz.
 2fC = 2  6880 * 100 = 1660 Hz.
Using a 1000 Hz cutoff 1st order low pass filter, f3 = 1000 Hz.
 2fC = 2  6880 * 1000 = 5245 Hz.
Observations:
The values of the Lock Range and Capture Range obtained by the experiment are:
Lock Range:
2fL = 8.4 kHz – 1.6 kHz = 6.8 kHz.
Capture Range:
Using a 100 Hz cutoff 1st order low pass filter,
2fC = 5.66 kHz – 4.37 kHz = 1.29 kHz
Using a 1000 Hz cutoff 1st order low pass filter,
2fC = 7.7 kHz – 2.7 kHz = 5.0 kHz
PLL With “Locked” Indicator
The circuit is connected as shown in the schematic. This is a method of indicating if a PLL is
in its “locked” condition. Since the output of the phase detector tends toward zero,
multiplication of the input signal by a 90 shifted VCO signal (QUAD) tends to be maximum.
The DC component of this maximum signal was used to light a L.E.D, indicating that it is in
the locked state. As connected, it was difficult to light the LED while the loop is in the locked
state. Hence, we swapped the TTL and the QUAD outputs of the VCO. Now we were able to
get the LED to light up when the PLL was in the locked state.
Figure 3 B (a) PLL with lock operation
Figure 3 B (b) Block parameters to implement a diiode
Figure 3 B (c) Block parameters of VCO Quad
Figure 3 B (d) Slider gain as part of the limiter
Figure 3 B (e) Input power spectrum
Figure 3 B (f) Input scope
Figure 3 B (g) Output power spectrum
Figure 3 B (h) Scope 2 reading
AM Detection without Transmitter Reference
PLL can have a rather narrow bandwidth. We could use this feature to “pick off” a carrier
signal from between the two side bands in the case of AM signals. The PLL is now locked on
to the carrier’s frequency. If the limiter were removed, the PLL would still be locked to the
carrier’s phase. Thus, we have a method for coherent demodulation for AM and DSB with a
small pilot carrier.
We rigged up a circuit for the AM / DSBSC transmitter. The carrier frequency was set for 5
kHz and modulated at 1 kHz. In the open loop condition, the VCO (used for the detection)
was set to approximately 5 kHz, which is close to the carrier frequency. The 2 nd LPF cut off
frequency was set to approximately 2 kHz. The loop was closed and the detector output was
observed.
The detector was able to receive the AM wave quite well at both 50% modulation and 100%
modulation.
figure 3 C (a) Modulated input
figure 3 C (b)Ouput before feeding it to the LPF
figure 3 C (c)Slider gain part of limiter
figure 3 C (d) Am detect spectrum analyzer
figure 3 C (d) Recovered Signal
Appendix I
Prelab
I A 1st order LPF is used in a PLL and has a magnitude response of :
| F(f) | = sqrt( 1 / 1 + (f/f3)2)
To show that the capture range is 2fc = 2 sqrt(fLf3)
In
KD
Fs
Ko VCO
Lock Range:
2L = 2 KT
T(s) = KT F(s) / S
Total loop gain = Kd A Ko
2fL = KT / 
Capture Range
 = RC where  = 1 / 2f3
2c = 2 sqrt(KT /  )
2 (2 fc ) = 2sqrt(2fL / (1/ 2f3)) = 2 sqrt((2)2 fL f3)
2fc = 2sqrt(fL f3)
A
II
Lock Range:
2fL = KT / 
Capture Range:
2fc = 2sqrt(fL f3)
Ka = 2V Ko = 2 kHz /v A = 1
f3 = 100Hz
KT = Kd A Ko = (2V) (2 x 103 Hz / V) (1) = 4kHz
Lock: = 2fL = KT /  = 4kHz /  = 1.273 k = 637 Hz
Capture: = 2fc = 2sqrt(fL f3) = 2sqrt(637x100) = 504.6 Hz --- fc = 252 Hz
III
VCO(t) = sin(wot +  )
VIN(t) = 0.2 cos(wot)
e(t) = 0.2 sin(wot + ) cos(wot) ; Km = 1
Kd = 0.2 at max
KT = Kd A K0 = (0.2)(2x103 Hz / V) (1) = 400 Hz
Lock: = 2fL = KT /  = 400 /  fL = 6306 Hz
Capture: 2fc = 2sqrt(fLf3) = 2sqrt(6306x100) fc = 80 Hz
Limter O/p: 4.72 Vpp
VCO O/p : 3076 Vpp
Multiplier’s Constant: 0.408
Kd = (4.72 / 2) x (3.76 / 2) x 0.408 = 1.81 V
Avg. VCO Conversion:  fo / Va = -2.08 kHz / V