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Display System
4.1) Introduction
If keyboards are the predominant means of interface to human input, then visual
displays are the universal means of human output. Display may be grouped into three
broad categories:
1. Single Light(s).
2. Single character(s).
3. Intelligent Alphanumeric.
Single light displays include incandescent and, more likely, LED indicators that
are treated as single binary points to be switched OFF or ON by the program, or, as in
digital IC kits used in laboratories.
Single character displays include numeric and alphanumeric arrays. These may be
as simple as the seven segment numeric display up to intelligent dot-matrix display that
accepts an 8-bit ASCII code to corresponding alphanumeric pattern.
Intelligent Alphanumeric displays are equipped with a built in Microcontroller
that has been optimized for the application. The individual light and the intelligent single
character displays are easy to use. A port presents a bit or a character and strobes the
device. The intelligent alphanumeric terminals are normally serial devices, which
receives data and decides what to be displayed. There are many examples for
alphanumeric terminals, any real time display system may be considered as intelligent
alphanumeric terminals.
The display unit designed here is designed to function as intelligent alphanumeric
display. It consists of 8-rows and number of columns that can be decided as per the
requirement. Considering cost, design complexity and other aspects, the display was
SIR M.V.I.T., DEPARTMENT OF
E&C
1999-2000
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decided to be modules of 8-rows and 32-columns. Many such boards can be connected
serially to form a N-column display where N is a multiple of 32.
The display unit can be divided into three units.
1. Column Driver
2.
Row Driver
3.
LED Matrix
For simplicity of system integration the column driver and LED matrix were
combined together. The units are explained in detail in the following pages.
The basic building unit is as shown below.
Fig 4.1: Basic Cell for Display
The LED glows when both the transistors are on. One transistor is connected to
row data, and the other is connected to the column data. Many such small units put
together forms the complete display unit.
4.2) COLUMN DRIVER & LED MATRIX.
The circuit diagram of column driver with the LED matrix is as shown in the figure 4.2.
SIR M.V.I.T., DEPARTMENT OF
E&C
1999-2000
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Fig 4.2: Circuit diagram for Column driver with LED matrix
SIR M.V.I.T., DEPARTMENT OF
E&C
1999-2000
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The LED matrix is arranged in 8 rows & 32 columns. In the LED matrix, all row
cathodes are shorted and given to row data input connector and all the anodes of each
column are shorted and given to the decoder. Therefore each row data is given to all the
columns and only one column is enabled at a time by suitably decoding. Since the LED
requires large current, transistors are used to drive the LEDs. The transistors and LEDs
are analog devices, from basic facts of electronics we know that a buffer is required
between analog and digital interface for impedance matching. To avail this requirement
the decoder chosen was 74LS156.
The 74LS156 is used as a 3 to 8 line decoder. Each 74156 drives 32 columns .All
the select lines for 74156 are made common. This results in enabling of every alternate
8th column. To enable only one column at a time two more address lines are used to select
only one 74156 at a particular instant. These two lines are connected to a 74138 decoder,
which is used as a 2 - 4 line decoder. Another line is used to select the 74138 which
results in the selection of the board, this feature is necessary when connecting many such
boards, with the design of present board a maximum of 3 boards can be connected, that is
a maximum of 96 columns. It was decided that each character be of 8 columns. The
maximum number of characters that can be displayed are 12.
Since 74156 is an active low device the transistors are chosen to be PNP. The
transistors used here are SK100. For a visible display of port A data rate has to be chosen
suitably.
PA7
--
PA6
--
PA5
CE
(74138)
PA4
B1
(74138)
PA3
A1
(74138)
PA2
C
(74156)
PA1
B
(74156)
PA0
A
(74156)
Table 4.1: The Decoding of the address of column is as shown below
Port A data
20H
21H
:
:
:
3D
3E
3F
Column Enabled
1
2
:
:
:
30
31
32
Table 4.2: Address of columns
Let us consider each decoder separately.
SIR M.V.I.T., DEPARTMENT OF
E&C
1999-2000
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74LS156
These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual
strobes and common binary-address inputs in a single 16-pin package. When both
sections are enabled by the strobes, the common address inputs sequentially select and
route associated input data to the appropriate output of each section. The individual
strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied
to input C1 is inverted at its outputs and data applied at C2 is true through its outputs.
The inverter following the C1 data input permits use as a 3-to-8-line decoder, or 1-to-8line demultiplexer, without external gating. Input clamping diodes are provided on these
circuits to minimize transmission-line effects and simplify system design.
Features and Applications:
 Dual 2-to-4-line decoder
 Dual 1-to-4-line demultiplexer
 3-to-8-line decoder
 1-to-8-line demultiplexer
Fig 4.3: Logic diagram & Function table of 74LS156
SIR M.V.I.T., DEPARTMENT OF
E&C
1999-2000
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74LS138
These Schottky-clamped circuits are designed to be used in high-performance
memory-decoding or data-routing applications, requiring very short propagation delay
times. In high-performance memory systems these decoders can be used to minimize the
effects of system decoding. When used with high-speed memories, the delay times of
these decoders are usually less than the typical access time of the memory. This means
that the effective system delay introduced by the decoder is negligible. The 74LS138
decodes one-of-eight lines, based upon the conditions at the three binary select inputs and
the three enable inputs. Two active-low and one active-high enable inputs reduce the
need for external gates or inverters when expanding. A 24-line decoder can be
implemented with no external inverters, and a 32-line decoder requires only one inverter.
An enable input can be used as a data input for demultiplexing applications. The
decoders/demultiplexers feature fully buffered inputs, presenting only one normalized
load to its driving circuit. All inputs are clamped with high-performance Schottky diodes
to suppress line-ringing and simplify system design.
Designed specifically for high speed

Memory decoders

Data transmission systems
74LS138 as 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading
and/or data reception
Fig 4.4: Function table & logic diagram of 74138
SIR M.V.I.T., DEPARTMENT OF
E&C
1999-2000
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4.3) Row driver
The circuit diagram of the row driver is as shown in fig 4.5:
Fig 4.5 Row Driver
A row driver is necessary to drive all the row LEDs. To drive the row LEDs each
row is connected to a transistor. As protection for the port providing the row data and for
impedance matching the port lines are passed through a buffer. The buffer used here is a
non inverting buffer that is 7407.
4.4) Summary
This chapter provides the detailed functioning of the display system. The software
section gives in detail about how the actual display on the display unit
SIR M.V.I.T., DEPARTMENT OF
E&C
1999-2000