A Novel CMOS Wideband Auto-tuning Phase Shifter Circuit
Saad M. Al-Shahrani
A novel auto-tuning phase shifter circuit suitable for integrated circuit implementation
is presented. The circuit exhibits simple structure and provides phase shifting over
three decades of frequency, 2kHz – 2MHz, with a minimal phase error, less than
3.5%. Simulation results using 0.5um CMOS technology and power supply ±2V are
included.
Introduction: Phase shifter circuit finds wide applications in instrumentation,
measurement, communication, and control systems. Literature shows different types
of phase shifter which includes frequency-dependent [1], frequency-independent [2],
and auto-tuning phase shifter [3-5]. The frequency-dependent phase shifter circuit
provides fixed or variable phase-shift at a single frequency. On the other hand,
frequency independent phase shifter provides a fixed phase shift over a wide range of
frequency. Although auto-tuning phase shifter can be used as an independentfrequency phase shifter, its main application is related to phase calibration. The
automatic phase shifter system presented in [3] is used to adjust the phase
misalignment in the Cartesian feedback linearization circuit of a power amplifier. An
auto-calibration circuit is commonly used in transceiver system to compensate gain
and phase mismatching [4]. In [5] an automatic phase calibration technique based on a
PLL is reported which is used to maintain the accuracy of the quadrature signals
generated. The major intention of this paper is, therefore, to present a new auto-tuning
phase shifter circuit which enjoys simplicity, accuracy, and wide frequency operation.
1
Proposed Circuit: The proposed phase shifter block diagram is illustrated in Fig. 1.
The input sinusoidal signal is processed through two paths: one includes a rectifier
circuit and attenuator while the second one includes 1st order allpass filter, and a
rectifier circuit. To define the overlapping period between the signals, and hence the
phase shift, a switch is inserted in the upper path which is controlled by the signal in
the lower path. The signals at the end of both paths are subtracted and the resulting
error signal e(t) is used to charge a capacitor; the generated capacitor voltage VC is
used to control the filter corner frequency ωo and thus the phase shift. The negative
feedback loop built in this circuit forces the error signal e(t) to go to zero which
occurs when the dc voltages V1 and V3 are equal. The operation principle of the
proposed structure is described in the following. Assuming ideal half wave rectifier
circuits, the dc components, V1 and V3, are given by:
V1 
V3 
k

(1)
I i Rx
1 - sin(  o  90
I i Rx
2
(2)
where θo is the phase shift, Rx is the input resistance of the differential element, and k
is the attenuation factor. By equating (1) and (2), at steady state when error signal e(t)
is zero, then
 o  90 o  sin 1 (1  2k )
(3)
From (3) phase shift θo can be controlled through the attenuation factor k which is
controlled by a ratio of two resistors. This adds an advantage to this design where
phase shift can be adjusted precisely independent of the process parameters variations.
Filter Circuit using MOCCII: Figure 2 shows the symbol and circuit configuration of
the multi output current conveyor (MOCCII). Ideal MOCCII can be modeled as
Iz1 = Iz2 = Iz3 = Ix,
Iy=0, Vx = Vy
(4)
2
Voltage buffer between Y and X terminal is built using a unity negative feedback opamp to reduce the voltage tracking error between these terminals. The filter block of
Fig. 1 is realized based on MOCCII as shown in Fig. 3. Routine analysis for the filter
circuit yields the following current transfer function of the first order allpass filter
(APF):
I o1
s  o

Ii
s  o
, where,
ωo= 1/(RC)
(5)
From (5) the filter's corner frequency ωo can be controlled through the grounded
resistor R. To add programmability feature to the filter, R is realized using two
MOSFET transistors operating in the ohmic region, see Fig. 4, which are
electronically tuned through voltage VC of Fig. 1. A simple analysis shows that, with
matched transistors, the nonlinearity of each transistor will be canceled by its counter
part. As a result a linear programmable resistor is obtained and given by:
R
(V1  V2 )
1

I
K o (Vn  V p  Vtn  Vtp )
(6)
where Ko and Vt are transistor's transconductance and threshold voltage respectively.
Equation (6) shows that R is linear resistor and can be controlled through biasing
voltages Vn and Vp. In our case, Vp is fixed at -0.9 V while Vn is adjusted through
voltage VC of Fig. 1. A simple single stage differential amplifier is used to subtract the
voltage signals V1 and V3 of Fig. 1. Each half-wave rectifier circuit of Fig. 1 is
realized using a single wide channel PMOS transistor biased at the edge of the triode
region to avoid large voltage drop across the rectifier terminals.
Simulation Results: To confirm the validity of the proposed structure, the circuit of
Fig. 1 was simulated with HSPICE using the CMOS MOCCII given in Fig. 3b. The
CMOS transistors were modeled by the 0.5µm BSIM3V3 CMOS models made
available through MOSIS. Fig. 5 shows the auto-tuning process with input signal Ii at
3
40 KHz and 0.5 attenuation factor k. As depicted in Fig. 5a the control voltage VC is
adjusted through the negative feedback loop, to set the error signal e(t) to zero, and
consequently R and filter phase θo are adjusted. According to equation (3) and with k
= 0.5, phase shift θo is equal to 90o which is confirmed by simulation as shown in Fig.
5b. Table 1 shows the performance of the proposed circuit at different attenuation
factors k with input signal at 40 kHz. Moreover, the proposed circuit is tested to
provide fixed phase shift of 90o over wide rang of frequency, 2kHz – 2MHz. Both
testes' results show good performance where phase error is less than 3.5% over wide
range of phase shift and frequency.
Conclusion: In this paper, a new CMOS auto-tuning phase-shifter circuit is presented.
The circuit exhibits a simple structure and provide wide phase shifting over three
decades of frequency with a minimal phase error, less than 3.5%. Simulation results
using 0.5um CMOS technology and power supply ±2V are included.
Acknowledgment: The author would like to thank King Fahd University of Petroleum for supporting the
work and Dr. Abuelma’atti for his valuable comments.
References
1
Chua, M., and Martin, K. : '1 GHz Programmable Analog Phase Shifter for
Adaptive Antennas'. IEEE Custom Integrated circuits conf. 1998, pp. 71-714
2 Sudhakar, K., Jagadeesh, V., and Sankaran, P. : 'Precision frequency-independent
variable phase phase shifter', Electronics Letters, 2nd Feb. 1995, vol. 31 no. 3, pp.
154-155
3 Dawson, J., and Lee, T. : 'Automatic Phase Alignment for a Fully Integrated
Cartesian Feedback Power Amplifier System', IEEE J. of Solid-State Circuits conf.,
2003, pp. 261-263
4 Yong, H., Wei, H., Shin, L., Chao, C., Wen, L., Sao, C., and David, C. : 'An autoI/Q calibrated CMOS transceiver for 802.11g', IEEE Journal of Solid-State
Circuits, November 2005, vol. 40, n 11, pp 2187-2192
4
5 Lee', D., Kim', C., and Hongl, S. : 'A Quadrature Signal Generator Using PLL
Technique', 33rd European Microwave Conf., 2003, pp. 777-780
Saad Al-Shahrani (Department of Electrical Engineering, King Fahd University of Petroleum and
Minerals, Dhahran, Saudi Arabia). E-mail: saadms@kfupm.edu.sa
5
Figure captions:
Fig. 1 The proposed phase shifter block diagram
Fig. 2 a) Block diagram of the multi output current conveyor symbol
b) Multi output current conveyor circuit configuration
Fig. 3 Current-mode first-order All-pass filter.
Fig. 4 Linear programmable resistor
Fig. 5 a) The control voltage VC over the tuning period.
b) Input and output signals after tuning.
Table 1: Phase of the output signal IO , at frequency= 40kHz.
6
Figure 1
AP Filter
1st order
IAP=Ii|θo Half Wave V2
Rectifier
Io=IA
Ii|0
V3
_
P
k
Half Wave
Rectifier
V1 +
e(t)
+
C
+
VC
-
Figure 2
IX
VY
IZ1
Z1
X
CCII Z2
IZ2
Z3
IZ3
Y
(a)
(b)
Figure 3
R
X
Ii
Y
Z1
CCII Z2
(1) Z3
X
CCII
Y (2)
Z1
Z2
Z3
C
Io1
Io2=-Io1
7
Figure 4
Vn
V1
I
V2
R
Vp
Figure 5
1.75V
1.50V
1.25V
1.00V
0s
5ms
V
V(Vr)
C
Time
10ms
15ms
(a)
Time
10 uA
500mV
0A
0V
-10 uA
-500mV
14.90ms
14.92ms
14.94ms
14.96ms
IV(V26:+)
I.95*V(Vap)
i
o
Time
Time
14.98ms 15.00ms
(b)
Table 1
k Io2-Phase (cal.) Io2-Phase (simul.)
0.12
40o
39.9o
0.25
60o
60.6o
0.50
90o
89.0o
0.75
o
120
117.6o
0.88
139.4o
136.8o
0.99
166o
164.9o
Error %
-0.10
1.03
-1.1
-2.00
-2.0
-1
8