SHAHABEDIN SHAHDOOSTFARD
PERSONAL INFORMATION
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Age : 23
Cell Phone : +98-912-5496551
Home Phone : +98-21-22840199
Email : shahab.shahdoost@gmail.com
EDUCATION
B.Sc.
Electrical and Computer Engineering Faculty,
Electrical Engineering Department,
2003 – 2007 Shahid Beheshti University, Tehran, Iran.
B.Sc. in Electrical Engineering (Microelectronics).
M.Sc. (In Progress)
Electrical Engineering Department,
Sharif University of Technology,
Master of science in Microelectronics.
LANGUAGES
TOEFL (IBT):
Listening: 29 ; Writing: 29 ; Reading: 28 ; Speaking: 19
Overall Score: 105
GRE GENERAL EXAM:
Verbal Section: 340 ; Quantitative: 790 ; Analytical Writing: 3
THESIS TOPIC & SCORE
B.Sc. : The usage of SET ( Single Electron Transistor) in MVL (Multiple-Valued Logic), under
supervision of Dr. Navi .
My B.Sc Thesis score is 18 out of 20.
A BRIEF B.Sc. THESIS EXPLANATION
To speed up a transistor, the main solution is to decrease it’s size.But, how much a transistor can
be shrinked? Complementary metal-oxide-semiconductor (CMOS) technology will face
significant technological limitations in the near future, and intensive studies are being conducted
in computational architecture, circuit design and device fabrication to find ways to overcome
this impending crisis.The main problem in CMOS technology is that the technology has arrived
on quantum boundaries.When speaking about quantum boudaries, we must have attention to
specific quantum effects and quantum phenomena.In other words, in quantum world the ordinary
rules would change, and common laws are not valid anymore.To overcome this problem many
new ideas have been suggested.One of the most remarkable substitution devices which are
suggested, are Single Electron Devices. Among these devices , single electron transistor is the
most important one.
It has two features that makes it really interesting to research and investigate on:
--Low power consumption
--Ultra Small Size
These two specific features, makes the single electron transistor suitable for ULSI (Ultra large
scale integration) technology, because the main obstacles in front of ULSI technology are size
and power consumption of NMOS and PMOS transistors.
The main focus of my thesis was on SET gates and majority gates made by single electron
transistors and the usage of these gates in Multiple Valued Logic. After I described the physics
governing the SET and the quantum phenomena in SET in first parts of my thesis, I introduced
the gate family made by SET. Then, I compared the common logic gate family (made by NMOS
and PMOS transistors) with this new suggested family in size and power consumptions.
Finally some adders made by SET gates were reviewed.In addition to size and power
consumption, in these new adders, the number of transistors used, have been reduced
significantly.
The thesis was warmly welcomed by my thesis supervisor, Dr. Keivan Navi , and other faculty
professors.
FIELDS OF STUDY AND EXPIRIENCE
RF Microelectronics, SET (Single Electron Transistor), Quantum Computing, QCA, VLSI,
CMOS(Analog Circuit Design), Communication Circuits, PLCs ( programing languages such as
ladder standard PLC language and…) ,
RESEARCH INTERESTS
Analog Circuit Design (CMOS), Radio Frequency & Microwave Commuinication Circuits,
Design of ADC and DAC, System On Chip Design (SOC) , VLSI, SET (Single Electron
Transistor), QCA( Quantum-dot Cellular Automata) and Quantom Computing.
SOFTWARE FAMILIRITIE S
Computer Programming Language: C++,C#.
Engineering Softwares: Matlab, Pspice, Hspice,ADS, Electric, Proteus, Pinnacle and AutoCAD.
General Software: Word, Excel, Powerpoint, …
INTERNSHIP
My 3-month period of internship was spent in IR-TCI (also known as MCI) ,
which is Iran’s first and the largest cellular phoneoperator ( This company is under
supervision of IRAN’s ministry of telecommunication.)
Activities : Afetr learning about GSM generations (by attending theory and preparation courses
and workshops), I took part in installing BTS sites, designing radio links, setting up radio links
between BTS sites and BSC centers, and replacing old HDSL cable links with new radio links .
JOB EXPERIENCES
Summer 2005: Two years after beginning of the bachelor program ,I took an informal internship
in PARS-ARC Co. which is the official representative of the SIEMENS Co. in IRAN and I began
to learn about PLC’s bascis and it’s programming. I also became familiar with BMS(Building
Management System) concepts.
Summer 2008: working in SARIAK ENG. CO.(This company is official representative of the
INDUSTRONIC Co. in Iran).
PROJECTS & SEMINARS
Seminar: Electronics & modern ceramic engineering, presented in Sharif University of
Technology as the seminar course in M.S. grade.(Under supervision of Dr. Rashidian)
Seminar: “A Fast settling 100dB OPAMP in 180nm CMOS process with compensation based
optimisation” , presenting an state-of-the-art op-amp, which was presented in JSSC 2008.(Under
supervision of Dr. Atarodi)
Seminar: MEMS sensors, focusing on “Liquid Flow Sensors”, under supervision of
Mazloom Nezhad (In the “Electronics Measureme" course) .
Dr.
Seminar: CMOS analogue circuits, focusing on “Active Loads”, under supervision of Dr.Jalali
(in the “CMOS Circuit Design” course) .
Project: simulation of a credit card (with proteus software) as 80x51 u-controller course and
implementing of the circuit on breadboard(as the u-controller lab project),it includes running of a
LCD and keyboard, with full operations of a real credit card.
SOME RELATED SCORES
Electrical Circuits II
(16.5)
(Rank the 1st student)
Electronics LAB I
(20)
(Rank the 1st student)
Electronics II
(17)
(Rank the 1st student)
Electronics LAB II
(20)
(Rank the 1st student)
Pulse Technique
(19)
(Rank the 2nd student)
Electronics LAB III
(20)
(Rank the 1st student)
Logical circuits LAB
(20)
(Rank the 1st student)
Physics of Electronics
(16)
(Rank the 1st student)
Power Electronics
(18.75) (Rank the 2nd student)
VLSI
(16.5)
B.Sc Thesis
( 18 )
(Rank the 2nd student)