Group-04
g04_testbed
Sonali Deshpande
Michael Dang’ana
260046793
110234458
DIGITAL SYSTEM
DESIGN
Lab Report 3
Using Altera Quartus II Software
g_04_testbed
Group-04
g04_testbed
Sonali Deshpande
Michael Dang’ana
260046793
110234458
Table of Contents
1.
2.
3.
4.
5.
6.
Description .........................................................................................................3
Pinout Diagram: ................................................................................................4
Schematic Diagrams..........................................................................................5
Discussion ...........................................................................................................7
Timing Performance Summary .......................................................................9
FPGA Resource Utilization Summary ..........................................................10
Group-04
g04_testbed
Sonali Deshpande
Michael Dang’ana
260046793
110234458
1. Description
This test-bed is a circuit that present inputs to a module and displays outputs of the
module in a way that lets it evaluate the performance of the module.
The following modules were tested with this circuit:
a. Pulse Generator
b. 0-25 Counter
c. 5:25 Decoder
d. Barrel Shifter
e. 25:5 Encoder
f. LED Segment Display
The Pulse Generator is a circuit that produces a repetitive pulse with a period of 0.3
seconds, and a width of one fast clock cycle (40 nsec if one uses the clock generator on
the Altera board). It will be used as the count_enable for the 0-25 counter.
The 0-25 Counter is a 5-bit counter that counts up from 0 to 25 and repeats. It uses
schematic capture and the Altera lpm_counter library module. Once it detects that the
counter has reached 25, it then loads the count of 0 on the next clock pulse (using
synchronous loading).
Our test-bed circuit has the following inputs and outputs:
Input: In[4..0], pulse_reset, count_reset, enable.
Output: Output [6..0].
Our Pulse Generator circuit has the following inputs and outputs:
Input: reset, enable, clock.
Output: pulse.
Our 0-25 Counter circuit has the following inputs and outputs:
Input: reset, count_enable, clock.
Output: Output[4..0].
Group-04
g04_testbed
Sonali Deshpande
Michael Dang’ana
2. Pinout Diagram:
Below is a simple diagram showing the inputs and the outputs of our circuit,
test_bed.
Below is a simple diagram showing the inputs and the outputs of our circuit,
Pulse Generator.
Below is a simple diagram showing the inputs and the outputs of our circuit,
0-25 Counter.
260046793
110234458
Group-04
g04_testbed
Sonali Deshpande
Michael Dang’ana
3. Schematic Diagrams
Test-bed
260046793
110234458
Group-04
g04_testbed
Pulse Generator
0-25 Counter
Sonali Deshpande
Michael Dang’ana
260046793
110234458
Group-04
g04_testbed
Sonali Deshpande
Michael Dang’ana
260046793
110234458
4. Discussion
With the intention of ensuring the efficacy of the circuit, we ran a comprehensive functional
simulation and verified the integrity of the subsequent results.
This was achieved through the use of a Vector Waveform File.
For each input the corresponding output was checked.
All our results produced precise outcomes.
Testing:
For the test-bed circuit, we tested the loading of the reset value, as well as the circuit’s ability to
produce the remaining characters of the alphabet in the right order. We also tested the toggle
back to letter A once the output reached letter Z. This allowed us to test how the individual
modules operated when placed in a circuit, as apposed to how they operated when alone. The
results can be seen in the simulation screenshots.
For the Pulse Generator circuit, we tested the division factoring of the main clock signal. This
allowed us to test the logic used to generate the ‘pulse’ signal. The results can be seen in the
simulation screenshots.
For the 0-25 Counter circuit, we tested the circuit’s ability to load 0 once 25 was reached. This
allowed us to test the logic used to generate the ‘sload’ signal of the counter. The results can be
seen in the simulation screenshots.
Simulation Screenshots:
Below are the screen captures of our simulation results of our test-bed circuit.
To convey the thoroughness of our circuit, we decided to include another screenshot from the
middle segment of the waveform. As you can see the pulse is set to one when the Output goes
back to A.
Group-04
g04_testbed
Sonali Deshpande
Michael Dang’ana
260046793
110234458
Below are the screen captures of our simulation results of our Pulse Generator circuit
The simulation was done for a pulse constant of 755 (instead of the required 7,552,499 which is
too large to be easily done within a short period of time) to demonstrate the division factoring of
the main clock signal, for at least one pulse cycle. This full cycle can be seen in the picture
below:
Below are the screen captures of our simulation results of our 0-25 Counter circuit
To convey the thoroughness of our circuit, we decided to include another screenshot from the
middle segment of the waveform. As you can see the Output is set to 0 when it reaches 25.
Physical Measurements:
We measured one aspect of the barrel shifter, namely, the propagation delay (tpd) between the
LSB of the input and the LSB of the output. We found that tpd = 130ns approx.
The measurement was done using the oscillators in the DSD lab.
Group-04
g04_testbed
Sonali Deshpande
Michael Dang’ana
260046793
110234458
5. Timing Performance Summary
The Diagram on the left gives the timing
analysis of the circuit produced by the
Timing Analyzer of the Compilation Tool of
Altera.
It shows the worst case propagation delay as
coming along the In[4] - Out[6] path. The
delay is 120 ns approx.
Group-04
g04_testbed
Sonali Deshpande
Michael Dang’ana
260046793
110234458
6. FPGA Resource Utilization Summary
Below is the summary as shown in the Altera compilation report of the test-bed circuit.
The total number of logic elements used is 349.
This concludes our 3rd Laboratory Report