EELE 414 – Introduction to VLSI Design Homework #13 Name: Grade: __________________________ _____ /20 You are going to design a combinational logic circuit using a Full Custom AOI/OAI approach. Your circuit should implement the truth table given below. ABC 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 | | | | | | | | | F 0 1 0 0 1 1 0 0 You will need to enter your entire circuit into S-edit and perform a functional SPICE simulation to verify its operation. You will then need to layout your entire circuit and successfully pass DRC & LVS. Hint 1: After finding the minimized Logic expression, you’ll need to manipulate it into a format that is suitable for AOI/OAI synthesis. It might be useful to perform a double inversion on your logic expression. Deliverables: a) Provide an S-edit transistor level schematic showing your logic circuit and your work for creating the CMOS circuit (i.e., logic manipulation, dual pull-up/down graphs, etc..). (4 Points) b) Provide a simulation waveform verifying your circuit behaves as intended. Again use 3 different pulse voltage sources to generate all possible input codes (000-001-010….111). You should create a symbol for your circuit with 3 inputs and 1 output. Within your symbol will be a large transistor level schematic. If you do it this way, you can leverage your top level test schematic from last week. (4 Points) c) Turn in a printout of your entire L-edit layout. (4 Points) d) Turn in a screenshot showing a successfully DRC. (4 Points) e) Turn in a screenshot showing a successfully LVS. (4 Points)