Lab 2: Getting Started with ICgraph
-by: Zheng Chen
-revised by: Sanjeev Gunawardena
-revised by: Liang Yin
-revised by: Richard K Wallace
Last Modified 7/23/99
INTRODUCTION:
This lab exercise introduces how to handcraft the layout for a simple inverter, using Mentor's
layout editor ICgraph. In full custom IC design, you must develop your own "standard cells"
which should have both schematics at the transistor (FET) level and layouts at the physical level.
We have created the schematic for my_inverter in the last lab, and here we'll craft a layout for it.
We will adopt a twin-well, 2 metal and 1 poly MOSIS Scalable CMOS process and design rules
(Rev. 7 with half lambda rules). Before going ahead, you should make a subdirectory
physical_lib under your $CLASS, where the layouts of cells will be stored.
PROCEDURE:
1) After logging into a workstation in Stocker 301, start running Mentor ICstation: by typing %
ic& at the command line. ICstation is Mentor Graphics' layout editing software toolset.
ICgraph is the heart of the ICstation environment. Set the working directory to $CLASS by
selecting the pull-down menu MGC>Location Map>Set MGC Working Directory....
Refer to the on-line document IC Station User's Manual for more details, especially, Chapter
17 Full Custom Editing Operations, and Chapter 27 Tutorial. To open the book, select the
pull-down menu Help>Open Bookcase.
2) The MOSIS Scalable CMOS (SCMOS) process and design rules have automatically been
loaded. You may notice the text Process: scmos3l (-R) at the upper-left corner of the
window, manually load the SCMOS process by selecting File>Process>Load... . Enter
$MGC_HEP/technology/ic/scmos in the dialog box and click OK. You may open the design
rules file by selecting MGC Notepad OpenRead-only... and entering
$MGC_HEP/technology/ic/scmos.rules as the file name in the dialog box.
3) Copy an existing via cell to your cell library by selecting the pull-down menu MGC>Design
Management> Copy Object.... In the dialog box, use the Go To button on the left to select
$MGC_HEP/lib/parts/ic/via, and enter [destination] with $CLASS/physical_lib/via. We'll
use this via cell later. Note: The Via cell is represented by the highlighted icon in Figure: 1.
This is the only file required for your physical_lib directory. A via is used to connect Metal 1
to Metal 2.
Figure 1: IC Station, Copy Object
4) Create a inverter cell by clicking on the [Cell]Create item on the session palette. In the
dialog box, enter Cell Name: $CLASS/physical_lib/MY_INV (same name as the comp
property value of the symbol, see lab 1), and select Angle Mode: Ninety and Connectivity
Mode: Polygom Editing. In the layout editor window, you may use the default strokes
(holding on the middle button of the mouse) to zoom in or out. Use menu Help On Strokes to
study the strokes for zoom-in, zoom-out, view-all, view-area, and unselect, etc.. When
zoomed in enough, it shows two kinds of grids, small and dim ones, as well as big and bright
ones. The small grid represents 0.5 lambda, while the big grid represents 5 lambda.
5) Type the command sho la p to show layer palette. In the dialog box, you may see all of the
layers defined in this process. We will only draw layouts on layers 2-3, 41-51, and 4104.
Close the dialog box. Type sho la p 2-3 41-51 4104 and return. The layer palette will be
shown on the right. Each layer has three switches "svf" to represent its selectability,
visibility, and fillability. Click the left button of the mouse on the layer to select it. Click the
middle button on the layer to toggle its visibility. Click the right button on the layer to toggle
its fillability.
6) Figure 2 represents a stick diagram of the inverter schematic. We will follow this diagram to
help create our inverter cell.
Figure 2 : Stick Diagram of Inverter
7) Port Creation - Ports are the external connections to the device. There are 4 ports for the
inverter VSS, VDD, IN and OUT. Note: there is redundancy to many of the options used in
IC Station. You can probably find the same command in the pull down menu's, the palette
and the pop up menus. For people who wish to become real speed-burners in IC Station,
middle click and draw a question mark across the screen to learn about IC graph Strokes.
a) Set the IC layer to Metal1.PORT by clicking on [Metal 1.PORT] layer on the sho la p
palette.Click on the [shape] button located in the [Easy Edit] palette.
b) Click and drag the cursor and make a square 3 x 3 lambda. You may wish to create a
ruler to determine the height and width of the square by using the pop up menu option
add>ruler. You can modify any shape by using the pop up menu edit>notch or edit>slice.
c) Use the pop up menu edit>copy and place three more squares.
d) Use the pop up menu edit>unselect>all.
i) Select one of the squares. This will be your VDD port.
ii) Add properties to the VDD port. The properties consist of a net name and a physical
pin name. The properties modify the design by making the layers visible in an
external aspect. When you include this cell in a hierarchy, you will only see the layers
with the associated properties. This is to help make things clear at higher levels of the
hierarchy.
iii) Change the cell to connectivity editing by using the pull down menu Context>Set
Cell Config>Connectivity Editing. Nets group together individual pieces of the cell
under a single label. This tells IC Station that the pieces are connected together.
iv) Add net to the Metal 1 port. Select [Add Object] Property Text * from the Easy
Edit palette. In the prompt bar, enter Property name: net and value: VDD. Open the
[options] form, then select layer metal1.port, change the [height] to 1, [Property
Owner] net, and click on [Keep options] settings button. Move the mouse to where
you want to put the text.
v) Add a port or physical pin to the selected item. Choose the popup menu
Add>Make>Port. In the prompt bar, fill [type] power, [direction] in, and [name]
VDD.
vi) Unselect the port and choose another to be port VSS. Use the method above to add
the properties to the port except the Property name: net, value: VSS and pin [name]
will now be VSS.
e) The last two ports will be the signal ports of IN and OUT.
i) Unselect the VSS port and choose another port without properties. Give the port
Property name: net, value: IN, and port [direction] in, [type] signal and [name]
IN.
ii) Unselect the IN port and choose the last port without properties. Give the port
Property name: net, value: OUT and port [direction] out, [type] signal and [name]
OUT.
FIGURE 3: Port Creation
8) Device Creation: Create the NMOS transistor with a width of four and a length of two using
the pop-up menu option Add>Device. Follow the hyper-link to learn more about device
creation. Note: The lengths and widths of the transistors are specified in Lab 1. All devices
you create must have their corresponding values specified in DA. If DA specifies different
values then any later device performance simulation will be incorrect. Highlight Specify
Name and hit [OK]. Input MN in the [Specify Name] window and hit [OK]. This means you
want an NMOS device while MP represents a PMOS device.
a) Enter [width] 4 and [length] 2.
b) Choose [Mos Transistor Types] nmos4. This represents a 4 terminal device.
c) Choose the [Source/Drain Contacts] option, both. This places a Source and Drain to
each side of the gate contact.
d) Place a 1 within the first [Gate Combinations] window and choose [OK] to place the
device. This specifies a single transistor.
e) Create a PMOS device that has a singular transistor with a width = 4, length = 2 and
place the device.
f) Rotate the PMOS device 180 degrees by selecting the pop up menu item
edit>rotate>180. This will place the drain of the PMOS device above the source of the
NMOS device (Refer to the stick diagram of Figure 2).
g) Activate the editor window, and select the [Easy Edit] item on the IC palette. Add a ruler
for properly placing the devices 9 lambda apart, by choosing [Add Objects] Rulers *
item. Note: look page 15 in book (Digital Integrated Circuits, Jan M Rabaey) for more
information on layout design rules. The devices must be separated by 9 lambda because
they are surrounded by wells of different potential.
Figure 4: NMOS and PMOS Device Creation
9) Connecting the devices to the ports using the stick diagram of Figure 2: This will assign
the source, drain and gate of the NMOS and PMOS devices to the nets you created for the
ports. Unselect all and then select the pin to the left of the gate (source pin) of the
NMOS device. Note: you should get a message similar to the message at the bottom of
Figure 4 ( Pin "s"... on a device "mn" ....). The gate is the red Poly line intersecting the
center of the device while the source and drain are the blue Metal pins to each side of the
gate.
a) Choose the pull down menu, Connectivity>Net>Add to Net option.
b) Choose [Select net name] VSS and press [OK] button and you should see a yellow
"overflow" line connecting the pin to the port.
c) Follow the stick diagram of Figure 2: to connect the remaining pins to their
corresponding ports.
Figure 5: Connecting the Device using the Stick Diagram
10) Creating Well Contacts:
a) Create nwell_contact. For the nwell_contact, you need to draw a 2L x 2L square of
contact_to_active, a 4L x 4L square of metal1 layer, a 5L x 5L square of active, a 9L x
9L square of n_plus_select, and a 12L x 12L square of n_well, which are overlapped.
b) Make the Metal 1 square a port named VDD.
Figure 5: Nwell Contact
c) Create the pwell_contact, do the same things except using p_plus_select and p_well layer
(use 11LX11L) instead of n_plus_select and n_well layer, and making port VSS instead
of VDD.
d) Notch the VDD and VSS ports using the pull down menu edit>notch to expand the port
to the width of each device and 12 lambda high.
e) Place the contacts within their respective Metal 1 port layers.
Figure 6: Well Contact Placement
11) Connecting the Device to the Ports using Poly and Metal 1.
a) Following the stick diagram of Figure 2 connect the drain of the PMOS device to the
VDD rail Use the property edit>notch>out to notch the rail over the drain contact..
b) Connect the source of the NMOS device to the VSS rail.
c) Create a 5 x 5 lambda square of Poly and use it to overlap a 2 x 2 lambda
Contact_To_Poly square. This contact is required to connect Metal 1 to Poly. Note: the
1.5 lambda overlap of Poly to Contact and refer to the design rules in the book.
d) Create a Metal 1 shape that overlaps the port IN to the Poly contact. Note: Notice the 1
lambda overlap of Metal to Contact.
e) Connect the gate Poly to the contact by notching the gate Poly. Note: Minimum Poly
width is 2 lambda.
f) Connect the source of the PMOS device to the drain of the NMOS device by a Metal 1
layer. Note: minimum Metal 1 width is 3 lambda.
g) Notch the Metal 1 strip to overlap the OUT port.
Figure 7: Final Cell
12) Finish this exercise by saving the cell File>Cell>Save Cell and closing IC station.
[ VLSI EE415 Lab Assignment ]