VLSI Lab Manual
VLSI LAB MANUAL (06ECL77)
Subject Code :
06ECL77
IA Marks : 25
No. OF Practical Hrs/Week : 03
Exam Hours : 03
Total no. OF Practical Hrs. : 42
Exam Marks : 50
ASIC-DIGITAL DESIGN FLOW
PART – A
DIGITAL DESIGN
1. Write Verilog Code for the following circuits and their Test Bench for verification, observe the
waveform and synthesis the code with technological library with given Constraints*. Do the initial
timing verification with gate level simulation.
i. An inverter
ii. A Buffer
iii. Transmission Gate
iv. Basic/universal gates
v. Flip flop -RS, D, JK, T
vi. Serial & Parallel adder
vii. 4-bit counter [Synchronous and Asynchronous counter]
viii. Successive approximation register [SAR]
* An appropriate constraint should be given
PART - B
Analog Design Flow
ANALOG DESIGN
1. Design an Inverter with given specifications*, completing the design flow mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimize Time, Power and Area to the given constraint***
2. Design the following circuits with given specifications*, completing the design flow
mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
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ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
i) A Single Stage differential amplifier
ii) Common source and Common Drain amplifier
3. Design an op-amp with given specification* using given differential amplifier Common
source and Common Drain amplifier in library** and completing the design flow mentioned
below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
4. Design a 4 bit R-2R based DAC for the given specification and completing the design flow
mentioned using given op-amp in the library**.
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check OF LVS
d. Extract RC and back annotate the same and verify the Design.
5. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and
verify the functionality by completing ASIC Design FLOW.
PART – A
DIGITAL DESIGN
Steps to use Xilinx tool:
Start the Xilinx Project Navigator by using the desktop shortcut or by using the
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 Start → Programs →Xilinx ISE → Project Navigator.
 In the Project Navigator window go to FILE →New project → Click on new source→
verilog module and give the name inverter.v → Define ports→ Finish
 Select devices → General purpose → Spartan 3 → ISE simulator → verilog
 In the create new source window select source type as verilog module give file name
 assign inputs and outputs → click next → finish→ yes → next → next → finish
 Double click on source file→ complete the verilog code for inverter
 Check syntax, and remove errors if present
 Simulate the design using ISE Simulator Highlight inverter.v file in the Sources in
 Project window. To run the Behavioral Simulation, Click on the symbol of FPGA device
and then right click→ Click on new source→ Click on verilog text fixture→ Give file
name with _tb→ finish
 Generate test bench file after initial begin assign value for inputs Click on simulate
 behavioral model → see the output.
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1.INVERTER
1. Write Verilog Code of an inverter circuits and their Test Bench for verification
Objective:
To design an inverter in verilog using xilinx tool and verify it on ISE simulator
Tools : Xilinx ISE simulator .
Symbol and truth table:
Design Description:
NOT gate, for example, will invert the data. NOT gate has 1 input and 1 output. Whatever
the value is at the input, the output will have the opposite value. If the input is a 1, the output is a
0. If the input is a 0, the output is a 1. B = ~A
Waveform:
VERILOG CODE
//Data flow model
module in1(a, b);
input a; output b;
assign b=~a;
endmodule
// Behavioural model
module in1(a, b);
input a;
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output reg b;
always @(a)
begin
b=~a;
end
endmodule
//Test bench structure
module iin_v;
reg a; // Inputs
wire b; // Outputs
// Instantiate the Unit Under Test (UUT)
in1 uut (.a(a),.b(b) );
initial begin
a = 0;
#100; // Wait 100 ns for global reset to finish
// Add stimulus here
a = 1;
#100; // Wait 100 ns for global reset to finish
end
endmodule
Waveform:
Conclusion: Design of an inverter is done using xilinx tool and is verified.
2. BUFFER
2. Write Verilog Code of a Buffer circuits and their Test Bench for verification
Objective:
To design a buffer in verilog using xilinx tool and verify it on ISE simulator.
Tools : Xilinx ISE simulator .
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Symbol and Truth table:
Design Description:
If we were to connect two inverter gates together so that the output of one fed into the
input of another, the two inversion functions would "cancel" each other out so that there would be
no inversion from input to final output: For this purpose, a special logic gate called a buffer is
manufactured to perform the same function as two inverters. Its symbol is simply a triangle, with
no inverting "bubble" on the output terminal: B = A
Waveform:
VERILOG CODE:
//Data flow model
module buffer(a, b);
input a;
output b;
assign b=a;
endmodule
// Behavioural
module buffer (a, b);
input a;
output reg b;
always @(a)
begin
b=a;
end
endmodule
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Waveform:
Conclusion: Design of a buffer in xilinx tool and is verified according to the truth Table.
3.Transmission Gate
3. Write Verilog Code of a transmission gate circuits and their Test Bench for verification
Objective:
To design a transmission gate in verilog using xilinx tool and verify it on ISE simulator.
Tools : Xilinx ISE simulator .
Circuit Diagram and Truth table:
A(Select)
0
1
1
IN
X
0
1
OUT
X
0
1
Design Description:
Transmission gate is an electronic element. It is a good non-mechanical relay, built
with CMOS technology. It can be used to simplify digital logic circuits or to switch analog
signals, and so is also known as an analog gate, analogue switch or electronic relay depending on
its use. It is made by the parallel combination of an nMOS and a pMOS transistor with the input at
the gate of one transistor being complementary to the input at the gate of the other transistor.
//VERILOG CODE
module transmission_gate(A,IN,OUT);
input A,IN;
output OUT;
wire Abar;
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assign Abar=~A;
pmos(OUT,Abar,IN);
nmos(OUT,A,IN);
endmodule
//Test bench code
module tg_tb_v;
reg A; reg IN; // Inputs
wire OUT; // Outputs
// Instantiate the Unit Under Test (UUT)
transmission_gate uut (
.A(A),
.IN(IN),
.OUT(OUT) );
initial begin
// Initialize Inputs
A = 0; IN = 0;#100;
A = 0; IN = 1;#100;
A = 1; IN = 0;#100;
A = 1; IN = 1;#100;
end
endmodule
Waveform:
Conclusion: Design of a transmission gate in xilinx tool and is verified according to the truth
Table.
BASIC GATES
4. Write Verilog Code of a Basic gates circuits and their Test Bench for verification.
Objective:
To design a basic gates in verilog using xilinx tool and verify it on ISE simulator.
Tools : Xilinx ISE simulator .
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AND GATE:
Symbol and Truth table of AND gate
Design Description:
The output of an AND gate is only equal to 1 if both inputs (A AND B in this case) are
equal to 1. Otherwise the output is equal to 0. The above picture shows a two input AND gate, but
an AND gate can have many inputs. In any case, no matter how many inputs it has, the output is
only equal to 1 if all the inputs are equal to 1, otherwise the output is 0.
The equation of an AND gate is: C = A & B
Waveform:
OR GATE:
Symbol and Truth table of OR gate
Design Description:
The output of an OR gate is equal to 1 if either input (A OR B in this case) is equal to
one. If neither input is equal to 1, the output is equal to zero. Again, the above picture shows a two
input OR gate, but an OR gate can have as many inputs as you like. The output will be equal to 1 if
any of the inputs is equal to 1.
The equation of an OR gate is: C = A + B
Waveform:
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EX-OR GATE:
Symbol and Truth table of XOR gate:
Design Description:
The output of an XOR gate is equal to 1 if either input (A or B in this case) is equal to
one, but equal to zero if both inputs are equal to zero or if both inputs are equal to 1. This is the
difference between an OR gate and an XOR gate, an OR gates output will equal 1 if both inputs are
equal to 1.
The equation OF an XOR gate is: C = A ^ B
Waveform:
NAND GATE:
Symbol and Truth table of NAND gate:
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Design Description:
A variation on the idea of the AND gate is called the NAND gate. The word "NAND" is
a verbal contraction of the words NOT and AND. Essentially, a NAND gate behaves the same as an
AND gate with a NOT (inverter) gate connected to the output terminal. To symbolize this output
signal inversion, the NAND gate symbol has a bubble on the output line. The truth table for a
NAND gate is as one might expect, exactly opposite as that of an AND gate:
As with AND gates, NAND gates are made with more than two inputs. In such cases, the
same general principle applies: the output will be "low" (0) if and only if all inputs are "high" (1). If
any input is "low" (0), the output will go "high" (1).
The equation of an XOR gate is: C = ~(A &B)
Waveform:
VERILOG CODE
//Data flow model
module gat(c,d,a,o,na,no,x);
input c,d ;
output a,o,x,no,na;
assign o=(c|d); //o -> or gate output
assign no=~(c|d); // no-> nor gate output
assign a=(c&d); // a-> and gate output
assign na=~(c&d); // na-> nand gate output
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assign x=(c^d); // x-> xor gate output
endmodule
//Test bench structure
module basi_v;
reg c;reg d; // Inputs
wire a; wire o; wire na; wire no; wire x; // Outputs
// Instantiate the Unit Under Test (UUT)
gat uut (.c(c), .d(d), .a(a), .o(o), .na(na), .no(no), .x(x) );
initial begin
c = 0; d = 0;#100;
c = 0; d = 1;#100;
c = 1; d = 0;#100;
c = 1; d = 1;#100;
end
endmodule
Waveform:
Conclusion: Design of Basic gates in xilinx tool and is verified according to the truth Table.
FLIP FLOPS
Objective:
To design Flip flops in verilog using xilinx tool and verify it on ISE simulator
Tools : Xilinx ISE simulator .
i) D FLIPFLOP
Symbol and truth table
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Design Description:
D Flip Flop has two inputs, the clock and the D input, and one output, Q. In the picture
D is connected to the node A, and Q is connected to the node B, so these are essentially names OF
the same thing. As can be seen in the truth table, the output is equal to the input on the rising edge
OF the clock. If there is no rising clock edge, the output will remain in its current state.
Waveform:
// VERILOG CODE
module d_ff( d, clk, q, q_bar);
input d, clk;
output q, q_bar;
reg q;
reg q_bar;
always @ (posedge clk)
begin
q <= d;
q_bar <= !d;
end
endmodule
//Test bench structure
module cc_v;
reg d; reg clk; // Inputs
wire q; wire q_bar; // Outputs
// Instantiate the Unit Under Test (UUT)
d_ff uut (.d(d), .clk(clk), .q(q), .q_bar(q_bar) );
initial begin
d = 0; clk = 0; #100;// Initialization of Inputs
d = 0; clk = 1; #100;
d = 1; clk = 1; #100;
d = 1; clk = 0; #100;
end
endmodule
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Waveform:
ii) T FLIPFLOP
Symbol and truth table
// VERILOG CODE
module t_ff ( t, clk, q, q_bar);
input t, clk;
output q, q_bar;
reg q;
reg q_bar;
always @ (posedge clk)
begin
q = ~t;
q_bar = ~q;
end
endmodule
//Test bench structure
module cc_v;
reg t; reg clk; // Inputs
wire q; wire q_bar; // Outputs
// Instantiate the Unit Under Test (UUT)
t_ff uut ( .t(t), .clk(clk), .q(q), .q_bar(q_bar) );
initial begin
t = 0;clk = 0; #100; // Initialization of Inputs
t = 0;clk = 1; #100;
t = 1;clk = 1; #100
t = 1;clk = 0; #100;
end
endmodule
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Waveform:
iii)SR FLIPFLOP:
Symbol and truth table
Design Description:
An SR Flip Flop is an arrangement of logic gates that maintains a stable output even after the
inputs are turned off. This simple flip flop circuit has a set input (S) and a reset input (R). The set
input causes the output of 0 (top output) and 1 (bottom output). The reset input causes the
opposite to happen (top = 1, bottom =0). Once the outputs are established, the wiring of the circuit
is maintained until S or R go high, or power is turned of to the circuit.
Waveform:
// VERILOG CODE
module sr_ff(clk,s,r,q,qb);
input clk,s,r;
output rer q,qb;
always @(clk,s,r)
begin
if(clk==1)
begin
if(s==0 & r==1)
begin
q=0; qb=~q;
end
else if(s==1 & r==0)
begin
q=1; qb=~q;
end
else if(s==0 & r==0)
begin
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q=q; qb=~q;
end
else if(s==1 & r==1)
begin
q=1'bz; qb= 1'bz;
end
end
end
endmodule
//Test bench structure
module rsff_v;
reg clk ;reg s; reg r; // Inputs
wire q; wire qb; // Outputs
// Instantiate the Unit Under Test (UUT)
ff uut ( .clk(clk), .s(s), .r(r), .q(q), .qb(qb) );
initial begin
clk = 0; s = 1; r = 0; #100; // Initialization of the Inputs
clk = 1; s = 0; r = 1; #100;
clk = 1; s = 1; r = 0; #100;
clk = 1; s = 0; r = 0; #100;
clk = 1; s = 1; r = 1; #100;
end
endmodule
Waveform:
IV) JK FLIP FLOP:
Symbol and truth table:
Design Description:
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The J-K flip-flop is perhaps the most widely used type of flip-flop. Its function is
identical to that of the S-R flip flop in the SET, RESET and HOLD conditions of operation. The
difference is that the J-K flip-flop does not have any invalid states. The logic symbol for the J-K
flip-flop is presented in Figure 3-8 and its corresponding truth table is listed in Table 3-5. Notice
that for J=1 and K=1 the output toggles, that is to say that the output at time t is complemented at
time t+1.
Waveform
// VERILOG CODE
module jk_ff(clk,j,k,q,qb);
input clk, j, k;
output q,qb;
reg q,qb;
always @(clk,j,k)
begin
if(clk==1)
begin
if(j==0 & k==1)
begin
q=0; qb=~q;
end
else if(j==1 & k==0)
begin
q=1; qb=~q;
end
else if(j==0 & k==0)
begin
q=q; qb=~q;
end
else if(j==1 & k==1)
q=~q; qb=~q;
end
end
endmodule
//Test bench structure
module jk_
reg clk, j, k ; // Inputs
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wire q, qb; // Outputs
// Instantiate the Unit Under Test (UUT)
jk_ff uut (.clk(clk), .j(j), .k(k), .q(q), .qb(qb) );
initial begin
clk = 0; j = 0; k = 0; #100;
clk = 1; j = 1; k = 0; #100;
clk = 1; j = 0; k = 1; #100;
clk = 1; j = 0; k = 0; #100;
clk = 1; j = 1; k = 1; #100;
end
endmodule
Waveform:
Conclusion: Design of Flipflops(D,T,SR,JK) in xilinx tool and is verified according to the truth
Table.
6. PARALLEL ADDER
6. Write Verilog Code of Parallel adder circuits and their Test Bench for verification
Objective: To design parallel adder in verilog using xilinx tool and verify it on ISE simulator
Tools : Xilinx ISE simulator .
Block diagram of parallel adder.
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Design Description:
Parallel adders are digital circuits that compute the addition of variable binary strings of
equivalent or different size in parallel. A number of full adders may be added to the ripple carry
adder or ripple carry adders of different sizes may be cascaded in order to accommodate binary
vector strings of larger sizes. For an n-bit parallel adder, it requires n computational elements
(FA). It is composed of four full adders. The augend’s bits of x are added to the addend bits of
y respectfully of their binary position Each bit 6 addition creates a sum and a carry out. The carry
out is then transmitted to the carry in of the next higher-order bit. The final result creates a sum
of four bits plus a carry out (c4).
VERILOG CODE
module padd(x,y, c, sum, cout);
input [3:0] x,y;
input c;
output [3:0] sum;
output cout;
FA stage0(x[0],y[0],c,sum[0],c1);
FA stage1(x[1],y[1],c1, sum[1],c2);
FA stage2(x[2],y[2],c2, sum[2],c3);
FA stage3(x[3],y[3],c3,sum[3],cout);
endmodule
// Function of full Adder
module FA(a,b,cin, s,c0);
input a,b,cin;
output s,c0;
assign s=a^b^cin;
assign c0=(a&b)|(b&cin)|(cin&a);
endmodule
// Test bench code
module aaa_v;
reg [3:0] x; reg [3:0] y; reg c; // Inputs
wire [3:0] sum; wire cout; // Outputs
// Instantiate the Unit Under Test (UUT)
padd uut (
.x(x),
.y(y),
.c(c),
.sum(sum),
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.cout(cout)
);
initial begin
// Initialize Inputs
x = 4'b0101;
y = 4'b1100;
c = 0; #100;
x = 4'b0001;
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y = 4'b1011;
c = 1; #100;
x = 4'b1011;
y = 4'b0101;
c = 0; #100;
end
endmodule
Waveform:
Conclusion: Design of Parallel Adder in xilinx tool and is verified according to the truth Table.
SERIAL ADDER
Aim: Verilog code for Serial Adder
Block diagram of serial adder
module sradd(a,b,start,clock,ready,result);
input a,b,start,clock;
output ready;output [7:0] result;
reg [7:0] result;
reg sum,carry,ready;
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integer count;
initial count = 8;
always @(negedge clock)
begin
if (start)
begin
count =0;
carry = 0;
result = 0;
end
else
begin
if (count <8)
begin
count = count + 1;
sum = a ^ b ^ carry ;
carry = (a&b)|(a & carry)|(b& carry);
result ={sum,result[7:1]};
end
end
if(count == 8)ready = 1;
else
ready = 0;
end
endmodule
Test bench for verification
module sradd_tb_v;
// Inputs
reg a;
reg b;
reg start;
reg clock;
// Outputs
wire ready;
wire [7:0] result;
// Instantiate the Unit Under Test (UUT)
sradd uut (
.a(a),
.b(b),
.start(start),
.clock(clock),
.ready(ready),
.result(result));
initial begin
// Initialize Inputs
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a = 0;
b = 0;
start = 0;
clock = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
End
Initial
Begin
clock = 1'b1;
a = 1'b0;
b = 1'b1;
#05 start = 1'b1;
#11 start = 1'b0;
#50 $finish;
End
always #2 clock = ~ clock;
always #3.1 a = ~ a;
always #5.1 b = ~ b;
endmodule
7.COUNTER
7. Write Verilog Code of counter circuits and their Test Bench for verification
Objective:
To design counter in verilog using xilinx tool and verify it on ISE simulator
Tools : Xilinx ISE simulator .
Circuit Diagram: 1) 4bit Up Counter:
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