ECE 551 - Digital System Design & Synthesis
Exercise 1 – Sections 2, 3, and 7 of IEEE Std 1364-2001 - Answers
Spring 2003
Write in the answer at A: for each of the following questions and bring to class on
Thursday, January 30 whether complete or not for use in the discussion.
1. Study sections 2.1 - 2.6.1, 2.7 - 2.7.4 of IEEE Std 1364-2001.
Comments
a. Write the word Verilog using the two forms for specifying comments:
A: // Verilog /* Verilog */
Constants
b. Write x11010011 in hexadecimal as a constant of size 12.
A: Since the base is not specified and an x appears, the base cannot be decimal,
so the answer cannot be determined. (If assumed binary, 12’hxD3. If assumed octal,
12’h009. If assumed hexadecimal, 12’h11.)
c. Write b x11010011 in hexadecimal as a constant of size 12.
A: 12’hxD3
d. Write – 16'hFFF in binary.
A: The question is ambiguous. The binary value of the given representation is:
000011111111111 = 1111000000000001. A binary representation can be
written as –16’b111111111111 or as 16’sb1111000000000001.
e. What is the decimal value of 8 shef?
A:  17
f. Write the following using sized hexadecimal with the hexadecimal digits grouped in
threes beginning at the right: 00010010001101000110100010011010
A: 0001_0010_0011_0100_0110_1000_1001_1010 becomes:
32’h12_346_89A or 32’H12_346_89A
Strings
g. What in the size of the reg in bits required to store the string “Jane Doe”?
A: There are 8 characters. 8  8 = 64
Identifiers
h. What are the only characters that can be used in a simple identifier other than letters
and digits?
A: _ and $
i. Is an identifier of length 1025 characters allowable?
A: Maybe. At least 1024 characters allowed for sure.
Keywords, System Tasks and Functions
j. All keywords must be lower case.
A: True False
k. Is the following in proper system function or system tasks format: $ stop
A: No. No space allowed after the $.
Compiler Directives
l. Where is the key located on a keyboard that you use for the open quote or accent grave
used to begin a compiler directive?
1
A: upper left
2. Study sections 3.1-3.7.2, 3.7.5 - 3.11 of IEEE Std 1364-2001.
Logic Values
a. Give the four basic Verilog signal values and their meanings
A: 0
A: 1
A: x
A: z
b. For normal logic gates, a z on a gate input is interpreted the same as an x.
A: True False
c. Can all of these values appear in non-faulty hardware? Explain your answer.
A: (values in 2 a) A qualified no. Generally, unknowns in simulations and don’t
cares in design represented by x become 1’s and 0’s in the hardware. Don’t cares acquire
0 and 1 values during the design process. Unknown values, e.g., at power up, are actually
0’s or 1’s that could be observed if desired. Beyond this, the matter of x in hardware
centers on what x really represents. In our logical models, x is a value that if applied to
the input of a not gate results in x on the output – in hardware, any input value on a gate,
due to high gate gain and system noise, results in a 1 or 0 on the output. Under this
definition, x does not exist. Under some other definition, perhaps it does.
Nets and Variables
d. Can a net store a value?
A: No, except a trireg net.
e. Can a variable store a value?
A: Yes, from one assignment to the next.
f. What are the variable datatypes?
A: reg integer real time realtime
g. What is the default initial value for variable datatypes?
A: For reg, integer, and time: x. For real and realtime: 0.
h. Give the scalar or vector declarations for each of the following:
1) Two vector registers, A and B, with bits numbering 7 to 0 from MSB to LSB.
A: reg [7:0] A, B;
2) Three scalar wires, enable, RESET, and run.
A: wire enable, RESET, run;
3) A wire mixed with bits numbered from –4 to 10. How many bits are there in
mixed?
A: wire [-4:10] mixed;15 bits
4) A designated three-state bus tbus with bit numbering 0 to 15 from MSB to
LSB
A: tri [0:15] tbus;
i. A variable is declared as follows. reg vectored [31:0] data_out;
data_out is referenced later in an expression as data_out[15:0]. Is this permitted?
Explain.
A: No. If a variable is vectored, a part of it cannot be referenced.
2
j. Circle the net type(s) can have multiple drivers:
A: tri wire wand
k. What assignment type can be used to assign a value to a reg type?
A: procedural assignments (blocking, non-blocking, continuous)
l. A variable of the integer type can be used for declaring a hardware register?
A: TRUE FALSE
m. A variable of the time type is used for simulation time quantities?
A: TRUE FALSE
Arrays
n. Write declarations for the following arrays:
1) A reg type array regfile with 32 8-bit registers .
A: reg[7:0] regfile[0:31]
2) A memory SRAM with 32 bit data size and a 14-bit address size
A: reg[7:0] SRAM[0:2**14  1]
reg[7:0] SRAM[0:16383]
Parameters
o. A parameter is a constant.
A: TRUE FALSE
p. Declare the codes for the states of a sequential circuit as a single parameter declaration
based on the following table:
State Name
State code
idle
00
brew
01
warm
10
unused
11
A: parameter idle = 2’b00, brew = 2’b01, warm = 2’b10,
unused = 11;
3. Study sections 7.1.1, 7.1.3 - 7.4, 7.14-7.14.1 of IEEE Std 1364-2001.
a. Specify in a single statement three instances of a NAND gate with the following
instance names and inputs and outputs:
1. g1 inputs: x1, x2 output n1
2. g2 inputs: x1, x3 output n2
3 g3 inputs: n1, n2 output z0
A: nand g1 (n1, x1, x2), g2(n2, x1, x3), g3(z0, n1,
n2);
b. What is the control value for which a bufif1 h as a z output?
A: 0
c. Specify a not gate with input x1 and output x2 with a delay of 5 time units.
A: not #5 (x2, x1)
d. Specify a not gate with input x1 and output x2 with a rising delay of 4 time units
and a falling delay of 2 time units.
A: not #(4,2) (x2, x1)
3
e. Specify a bufif1 gate with input x1 and output x2 (also needs enable) with a rising
delay of 6 time units, a falling delay of 3 time units, and a turn-off delay of 4 time units.
A: bufif1 #(6,3,4) (x2, x1, e)
f. Specify a NOR gate with inputs x1 and x2 and output z0 with 1) a rising delay of 6
time units max, 5 time units typical and 4 time units minimum, and a falling delay of 3
time units maximum, 2.5 units typical, and 2 units minimum.
A: nor #((6,5,4),(3,2.5,2)
4