Novel receiver for parallel optical chip interconnects
Maarten Kuijk, Daniel Coppee, Johan Stiens, Jan Genoe and Roger Vounckx.
ETRO/LAMI, University of Brussels
The traditional telecom receiver consists of several stages, typically a transimpedance
stage, AC-coupled with limiting amplifier stages, and sometimes autogain and offset
cancelling circuits. They rely on the assumption that the transmitted data is DCbalanced. The DC value of the photocurrent signal serves then as the decision level
for a final comparator that will determine whether logic “HIGH” or logic “LOW” has
been received. For single channel applications, a large area can be devoted to the
layout of the circuitry and even the power dissipation level is uncritical. In other
words, for single channel telecom applications the boundary conditions are not very
stringent.
However, DC-balancing of incoming data requires typically that 11 bits be
transmitted for every 8 bits of effective data. The effective bandwidth reduces, and
considerable Silicon real estate is required for this coding. Moreover the
transformation for this coding costs time, and adds to the latency. For single channel
telecom applications this overhead is not a concern. On the contrary, for most parallel
optical inter-chip interconnect applications this coding overhead, including the latency
is unacceptable.
The way signals are amplified and the received data reconstructed have therefor to be
changed considerably. The novel circuit we present uses a differential transimpedance
amplifier followed by a cascade of differential limiting amplifiers, and a differential
data reconstruction circuit. The limiting amplifiers are of a type that do not amplify
DC components, and hence -most importantly- they do not amplify offset mismatches
between pairing transistors. The highly non-linear decision circuit is smart enough to
reconstruct from the final amplified signal the original uncoded data sequence with
low latency, and low jitter. Digital DC data (e.g. millions of consecutive “0”s) can be
transmitted without problem. The filtering of the offset mismatches induces also
improved array homogeneity and guarantees CMOS yield. The exact operation of the
different parts will be discussed.
These receivers were monolithically combined with Spatially Modulated Light
detectors on a 100 micron pitch in X and Y direction, in a 10 x 10 array. They show
following merits (in 0.6 micron technology and at the maximum bit rate of 250
Mbit/s): average light input power (for BER < 10^-12, and PRBS 2^15-1) of 6.8
micro Watt; power dissipation per channel 2.3 mW; 200 ps channel to channel output
delay variation: good dynamic range (from 6.8 to 50 microWatt); no biasing
terminals; high array homogeneity (o.a. 100% yield on array of 100 elements), and the
capability to transmit DC data.
Optical interconnects based on this type of receiver make an optical interconnect very
similar to an electrical one. No coding, clocking or serializing (and deserializing) is
required. This hopefully lowers the threshold for digital designers to start using
optical interconnects in future.