Test vector ordering technique
The task of the reordering of patterns in the test set is to reduce the switchingh activity
during the test session [1-4].The paper [1] layed out the theoretical foundation for the power
constraint test scheduling problem. Circuits containing BIST hardware were discussed. The
objective was to minimize the total test length subject to power constraint. In [2] two
techniques for reducing power dissipation during test application, when scan test structure is
used, was proposed. The first one considered test vector ordering, the other one scan latch
ordering. In [3] a technique was proposed to reduce the internal switching activity by
lowering the transistion density at circuit inputs. Compared to the method in [2] the technique
in [3] is more time-efficient. In [4] the same problem of reordering test patterns was solved
for the case when don’t cares in test patterns are present. It was shown that the resulting
power savings due to pattern reordering using don’t cares can be significant. Both latter
methods [3,4]assume a high correlation between switching activity in the CUT and the
Hamming distance [4] or transition density [3] at circuit’s primary inputs.
Let T = (T1, T2,... Tn) be a given sequence of completely specified test patterns. Let S =
(S1, S2,... Sn) be a sequence of simulated signal values on all of the circuit’s nodes obtained as
the result of simulating the test vectors of T. The problem of power reduction during testing
can be formulated as the task of reordering the test patterns in T such that the overall power
consumption is minimized. This problem can be reduced to the (euclidean) travelling
salesperson problem (TSP )[5].
The argument is that the power consumption between every possible input-vector pair
(Ti, Tj) can be heuristically approximated by the Hamming distance between the input vectors.
Another hypothesis is that by minimizing the switching activity at the inputs we will also
minimize the switching activity on internal nodes of the circuit [3,4]. However, this
assumption is not always true, because one transition in a given input may cause many
transitions in internal nodes, whereas several inputs changing may cause fewer transitions.
To achieve more accurate results compared to [3,4] the switching activity at all internal
nodes of the circuit should be taken into consideration. The cost we have to pay for that is the
increasing cost of computation in reording the test vectors..
In this paper we present a new heuristic approach which aims at further increasing the
speed of reordering test patterns to achieve low power consumption. Increased speed of the
computation may allow us to take into account the switching activities at all internal nodes
instead of only at primary inputs. The approach is a modification of the greedy algorithm
where the search space is reduced.
The problem considered targets an optimal test pattern ordering of a given test sequence
T = (T1, T2,... Tm) such that both the average power and the peak power dissipation in the
circuit are minimized.
To solve the problem, consider a complete undirected graph G = (V,E) in which each
vertex Vl  V represents a test vector of T, and each undirected edge Ei,j = (Vi, Vj)  E
represents a pair of test vectors. The weight on each edge Ei,j represents the cost in terms of
switching activity of the application of the pair Ei,j to the circuit.
Let the number of primary inputs of the circuit is n, and the number of nodes of the
circuit (including primary inputs) is p.
The weight on edge Ei,j = (Vi, Vj) can be formally defined as
n
W ( Ei , j )   vi ( x k ) v j ( x k )
(1)
k 1
where vi(xk) represents the value of the node xk in the circuit when the test pattern Ti  T is
applied to the circuit, and vj(xk) represents the value of xk when the test pattern Tj  T is
applied to the circuit.. The Boolean difference vi(xk)  vj(xk) is equal to 1 if there is a
transition on the node xk between Ti and Tj, and 0 otherwise. In other words, the weight on
each edge of the graph G is obtained by summing the values of the switching activity in the
circuit after application of the test pair Ei,j = (Vi, Vj). The formula (1) corresponds to the
simplified case when only switching activities on inputs are taken into account [3,4]. By
substituting in (1) n with p we get the formula for calculating the weights for the exact case
when the switching activities at all the nodes of the circuit are taken into account.
Computation of the optimal test pattern ordering that minimizes the power dissipation
during test application can be regarded now as finding an Hamiltonian path of minimum cost
in the complete graph G. The cost of the path is obtained by summing the weights of the
edges belonging to the path.
This problem is equivalent to the well-known travelling salesman problem (considered as
NP-hard problem) for which different polynomial-time approximation algorithms can be used
[5]. Among these solutions, greede algorithms represent a good tradeoff between computation
time and efficiency of the achieved solution.
The power consumption between every possible input-vector pair (Ti, Tj) can be
heuristically approximated by the Hamming distance between the input vectors (in the
simplified case) or between the corresponding simulation vectors (Si, Sj) in the more exact
case. Since n >> m, the task of optimizing the order of vectors in T will be more realistic than
optimizing the order of vectors in S.
1) reordering test vectors based on transition density [45]
at circuit's primary inputs plus reducing the searching area;
(additional advancements in speed of calculation)
2) reordering test vectors based on switching activities
in the CUT plus reducing the searching area (here we are competing
with [38,45,50]).
References
[1] R.M.Chou, K.K.Saluja. Power constraint Scheduling of Tests. IEEE Int. Conf. on VLSI
Design, pp.271-274, 1994.
[2] S.Chakravarty, V.P. Dabholkar. Minimizing Power Dissipation in Scan Circuits During
Test Application. IEEE Int. Workshop on Low Power Design, pp. 51-56, April 1994.
[3] P.Flores et al. Assignment and reordering of incompletely specified pattern sequences
targeting minimum power dissipation. Proc. IEEE Int. Conference on VLSI Design,
pp.37-41, 1999.
[4] P.Girard et al. A test vector ordering technique for switching activity recuction during test
operation. Proc. IEEE Great Lakes Synposium on VLSI, pp. 24-27, 1999.
[5] D.S.Johnson, L.A.McGeoch. The travelling salesman problem: A case study in local
optimization. In “Local Search in Combinatorial Optimization”. E.H.L. Aarts, J.K.Lenstra
(eds.), John Wiley and Sons, 1996.