1. Extraction of the specific current I
S
Using the current-based model for the long-channel MOSFET in Fig. 1, one can readily prove that: d
 ln( I
D

 dV
X
1 dI
D
I dV
D X
 

2
 i
 i t f r



1 i f
 t dI
R
2 I dV
S X


Additionally, if the MOS transistor operates in saturation, e.g., V
Y
=V
DD
(1) can be written as: d
 ln( I
D

2 dV
X
 
 t

1 i 1
 whereas for V
Y
=V
X
+
 t
/2, (1) can be written as: d
 ln( I
D
 dV
X
 
 t

1
2 i 1
 i r

Expression (2) equals -1 deep in weak inversion ( i f
<<1) and equals -0.5 for i f
=8 ( I
F
=I
D
= 8 I
S
).

Use the circuit in Fig. 1 with both V
Y
=V
DD
and V
Y
=V
X
+
 t
/2 to determine I
S
for the nominal V
T 0
.

Set V
G
= nominal V
T 0
and measure the normalization current from both (2) and (3).
MY NOTE: Where do I get the nominal Vt?
MY NOTE: Set V
G
= nominal V
T 0
and measure the normalization current from both (2) and (3).
Use Vt determined from 8*Is in the first lab.
V
Y
(1)
(2)
(3)
I
D
V
G V
X
Fig. 1- Extraction of I
S
from g ms
/I
D

1.2. Using the methodology described in reference [5], find I
S
and V
T 0 of the MOSFET.

Plot I
D
vs V
G
and g mg
/I
D
vs V
G
.

Your measurements should range from at least i f

0.01 to i f

100.

What is the thermal voltage associated with your measurements?

What is the approximate value of n in weak inversion? Don’t forget to register the temperature while you are taking the measurements.
MY NOTES: Measure plateau level. This allows you to find n and If. Then do the Vt extraction.
2.
Extraction of V
P
If the drain current is set to 3 I
S
, as shown in the circuit of Fig. 2, then V
P
= V
S
. For V
S in the range –0.2V to approximately 6 V, plot the curve V
S
( V
P
) versus V
G
. Determine the value of V
T0
. Also plot n
  dV
P
/ dV
G
 
1
.
Fig. 2: Circuit for the extraction of V
P
and n.
3. Write a technical report. Due date is July 14 . You are expected to comment on the results and compare results with theory.
References:
[1] A. I. A. Cunha, M. C. Schneider and C. Galup-Montoro, "
An MOS Transistor Model for Analog Circuit Design
", IEEE
J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, October 1998.
[2] C. Galup-Montoro and M. C. Schneider, MOSFET Modeling for Circuit Analysis and Design , WSP, Singapore, 2007.
[3] M. C. Schneider and C. Galup-Montoro, CMOS Analog Design Using All-Region MOSFET Modeling , Cambridge University
Press, Cambridge, 2010.
[4] C. Galup-Montoro, M. C. Schneider, and A. I. A. Cunha, “ A Current-Based MOSFET Model for Integrated Circuit Design”,
Chapter 2 in Low-Voltage/Low-Power Integrated Circuits and Systems, edited by E. Sánchez-Sinencio and A. Andreou, IEEE
Press, 1999, ISBN 0-7803-3446-9.
[5] A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, C. D. C. Caetano, and M. B. Machado,
"Unambiguous extraction of threshold voltage based on the transconductance-to-current ratio"
, Workshop on Compact Modeling, Anaheim,
USA, Proceedings of Nanotech 2005, pp.139 - 141, May 2005.
[6] Technical reports: i. Fabiano Luz Cardoso – CNPq 1999 ii. Luiz Henrique Spiller – CNPq 2001 iii. Rafael Matos Coitinho – CNPq 2001