CEG 360/560 - EE 451/651
Lab 2
Dr. Doom
Lab 2: Sequential Circuit Analysis and Design
CEG 360/560 - EE 451/651
PURPOSE
The purpose of this lab is to analyze, design and build simple sequential logic circuits using flip-flops. This
is a two-week lab.
PRELAB (WEEK ONE): Sequential Circuit Analysis
(10 pts.) The goal of the first week is to analyze a pair of simple sequential circuits.
1) (3 pts.) Analyze the clocked sequential circuit shown in the logic diagram labeled Figure 1.
(a) Write logic equations for the signals D0 and D1, each as a function of the current value of the flipflop outputs Q0 and Q1.
(b) Draw (by hand) a functional timing diagram showing CLK, Q0 and Q1 for eight cycles of CLK,
assuming the circuit starts with Q0, Q1=00 and assuming that the duty cycle (percentage of time
high) of 50%. Remember that at each rising edge of the clock, the edge triggered D flip-flop simply
transfers the value on its D input to its Q output.
(c) How is timing diagram affected if the clock has a duty cycle of 25% or 75%
(d) What does this circuit do? Construct a truth table and a state diagram for this circuit. Consider how
the frequencies of the signals at Q0 and Q1 are related to the frequency of CLK. What are the duty
cycles of Q0 and Q1?
(e) Implement and simulate this device on the lab simulator. (Note: in order to implement the D-type
flip-flop using Foundation 2.1i software, simply use the FD primitive from the library and use an
INV (inverter) to generate the /Q output).
(f) Simulate the circuit described using the specified devices. Verify the timing diagram of the circuit
vs. your hand-drawn diagram. Include the simulation timing waveform printouts in your lab book
report.
2) (3 pts.) Analyze the clocked sequential circuit shown in the logic diagram labeled Figure 2.
(a) Draw (by hand) a functional timing diagram showing MCLK, Q1, /Q1, /P1, and /P2 for four cycles
of MCLK, assuming that the circuit starts with Q1 = 0 and that MCLK has a 50% duty cycle.
(b) How is the timing diagram affected if MCLK has a duty cycle of 25% or 75%?
(c) What does this circuit do (or, what is the relationship between the inputs and outputs)? Consider
how the frequencies of the signals at /P1 and /P2 are related to the frequency of MCLK. Determine
their duty cycles for all three of the duty cycles of MCLK mentioned above.
(d) Draw, print, and turn in a schematic for this circuit using D-type edge-triggered flip-flops and other
devices as necessary. Save (archive) your files but do not turn in a disk. Also include simulation
results in your lab book.
3) (4 pts.) Provide timing information for the sequential circuit shown in the logic diagram labeled Figure
3. Provide the timing information for the device:
(a) Setup time, EN input to clock:
(b) Hold time, EN input to clock:
(c) Propagation delay, clock to output (min):
(d) Propagation delay, clock to output (max):
(e) Maximum clock rate of device:
IN-LAB (WEEK ONE)
(5 pts.) Demonstrate your simulated circuits to your lab instructor. Be prepared to use these circuits to
generate a signal with a frequency and duty cycle announced by your instructor during lab. You will need to
determine which output of which circuit at what external clock frequency provides the signal specified.
Page 1 of 4
CEG 360/560 - EE 451/651
Lab 2
Dr. Doom
PRELAB (WEEK TWO): Sequential Circuit Design
1) (7 pts.) The goal of the second lab is to design a clocked synchronous state machine with two
synchronous inputs (X and /RESET) and two outputs (ZEROS and HALT) that realizes the following
operation.
 Whenever /RESET is asserted, the state machine will return to (or remain in) its START state
on the next clock tick, regardless of the value of X.
 A new value of X is assumed to arrive at each clock tick. If three Xs in succession are 0, the
output ZEROS should be immediately asserted.
 As long as /RESET is not asserted, the state machine continues to search for the three-0 pattern
and to assert ZEROS whenever it is found.
 /RESET does not directly affect the value of ZEROS when asserted (although the transition to
the START state will affect ZEROS).
 Overlap of patterns is allowed with one major exception, after X is 1 four times in succession,
the state machine will halt (stop searching for 0s) and assert the output HALT. HALT will
remain asserted and the data on X will be ignored until /RESET is again asserted
Clock
X /RESET
ZEROS HALT
00
00
01
01
00
10
01
10
00
10
01
00
Note: a / as the first character of a signal name indicates that the signal is active low. Thus, /RESET is
asserted (and thus resets the system) on a zero input.
(a) Which output or outputs are Mealy and which are Moore?
(b) Draw a state diagram or a state/output table for this machine. There should be seven states.
(c) Make a reasonable state assignment and construct the transition/output table for your state machine,
using three D-type edge-triggered flip-flops labeled Q2, Q1, and Q0.
(d) Draw, print, and turn in a schematic for the circuit using three D-type flip-flops and extra
combinational logic as necessary (be efficient!) Provide complete documentation and simulation
results for this schematic. Save/archive all files (to floppy or via FTP) but do not turn in a disk.
2) (3 pts.) Add a third (Moore) output, ZCOUNT, to your state machine. This output should report the
total number of 0s (mod 4) that have arrived since the last de-assertion of /RESET. 0s that occur while
the system is halted or while /RESET is asserted do not count. Draw, print, and turn in a schematic and
simulation results for the circuit, including documentation describing your implementation. Be certain to
save/archive your files (to floppy or via FTP).
Page 2 of 4
CEG 360/560 - EE 451/651
Lab 2
Dr. Doom
3) Graduate students only: Create and implement a circuit that generates “pseudo-random” bit-stream.
This bit-stream will be used to test the functionality of the circuits that you designed in parts 1 & 2. You
should use a counter with some logic to realize this circuit. Remember that there are two inputs that you
should generate with this circuit. Make sure the bit sequences produced by your design will give all of
the conditions that can be analyzed by the circuit from parts 1 & 2. Be sure to include schematic
printouts, simulation results, and appropriate documentation in your lab book report.
IN-LAB (WEEK TWO)
(5 pts.) Demonstrate the correct operation of your clocked synchronous state machine design. Completely
verify the operation of the circuit and simulation to your laboratory instructor. Be prepared to answer
questions regarding your documentation and the design process. Graduate Students are expected to
demonstrate that their circuit from part #3 can be used to generate adequate test patterns for the circuits from
parts 1 and 2.
Page 3 of 4
CEG 360/560 - EE 451/651
Lab 2
Dr. Doom
DFF
NAND
NOR
Timing Specification Information
Propagation Delay, Clock to Output (max):
Propagation Delay, Clock to Output (min):
Setup Time, Data input before Clock:
Hold Time, Date input after Clock:
Propagation Delay, Input to Output (max):
Propagation Delay, Input to Output (min):
Propagation Delay, Input to Output (max):
Propagation Delay, Input to Output (min):
Page 4 of 4
15 ns
12ns
10ns
2 ns
8 ns
3 ns
11 ns
5 ns