Manual of compact models for In-Plane Magnetic Anisotropy
(IP) Racetrack Memory (RM)
SPINLIB: Model IP_RM
Y. Zhang, W.S. Zhao, Y. Lakys, J-O. Klein, J-V. Kim,
D. Ravelosona and C. Chappert
IEF (Université Paris Sud/CNRS UMR8622)
Contact: weisheng.zhao@u-psud.fr
Table of contents
I. General Introduction
II. Files Provided
III. Parameters
III.A CDF
III.B Technology Parameters
III.C Device Parameters
I.
General Introduction
Current-induced domain wall (DW) motion in magnetic nanowires drives the
invention of a novel ultra-dense non-volatile storage device, called “racetrack
memory”. By combining this shifting scheme with magnetic tunnel junction (MTJ) for
reading and writing processes, it opens new routes for nonvolatile logic and memory
applications that are crucial for the future of spintronics. This manual reports on a
compact model for In-plane magnetic anisotropy ‘‘Racetrack memory’’ (IP RM). It
integrates spin transfer torque mechanism for magnetization reversal and domain
wall nucleation, current-driven domain wall pinning/motion behaviors, and tunnel
resistance theory of MTJ nanopillar, in which the free layer is one storage element of
magnetic stripe. This model is programmed with a very flexible structure to achieve
the best simulation precision and efficiency, and provide easy parameter
configuration interface. It is compatible with classical computer-aided design
environment and can be cosimulated directly with CMOS design kits. By using the
compact model, we have successfully simulated a ‘‘Racetrack memory’’.
Programmed with Verilog-A language
Validated in Cadence 6.1.5 Spectre, CMOS Design Kit 40nm.
The objective of this guide is to provide an easy way to start the simulation of hybrid
IP RM/CMOS circuits.
(a)
(b)
Fig.1. (a) Current induced IP domain wall propagation in a long CoFeB magnetic stripe; MTJs are used
as write and read heads for nucleating and detecting the magnetization. (b) The cross-section
structure of racetrack memory. At the back-end process, the magnetic stripe is implemented above
the CMOS/ MTJ interfacing circuits, which generate Iread for reading, Iwrite for domain wall
nucleation and Ipropagation for domain wall propagation.
II.
Files Provided
Decompress the compressed file IPRM40nm.tar which you have downloaded.
There are some files included in the file decompressed:
One file named “modelreadhead” includes a file of the type of veriloga which is the
source code of model of the MTJ for sensing, and a symbol file for this model;
One file named “modeltrack” includes a file of the type of veriloga which is the
source code of model of the magnetic stripe for propagation, and a symbol file for
this model;
One file named “cellreadhead” includes a package schematic of sensing IP MTJ and a
symbol file of this IP MTJ.
One file named “celltrack” includes a package schematic of DW and a symbol file of
this part.
(a)
(b)
Fig.2 (a) Symbol of sensing IP MTJ (b) Symbol of DW
One file named “cellwritehead” includes a package schematic of a IP MTJ as write
head and DW nucleation circuit, and a symbol file of this IP MTJ.
(a)
(b)
Fig.3 (a) Schematic of internal circuit of DW nucleation circuit (b) Symbol of DW nucleation circuit
One file named “Ipulse” includes a package schematic of propagation current
generator and a symbol file of this current generator.
(a)
(b)
Fig.4 (a) Schematic of internal circuit of propagation current generator (b) Symbol of propagation
pulse generator
Another file named “simu” is a test simulation with the model which demonstrates
how it works. For example, a IP RM (see Fig.5) has been simulated. The number of
bits depends on the length of track, for this simulation, length for 1 bit is 100 nm,
you can change this parameter to other values according to the requirement. One
“cellwritehead” works as write head to nucleate and switch the DW. After the
nucleation, the propagation current induces DW motion. Two sensing MTJ
(“cellreadhead”) working as read head is located 5th and 14th bit after the write
head.
Fig.5 Schematic of the test simulation
The result of transient simulation of this IP RM is shown in Fig.6. A 95uA at 2ns with
66 MHz frequency pulse works as the propagation current and shifts the DWs from
write head to read head. We can find out that the same pattern is obtained at the
read head after 5 and 14 pluses.
Fig.6 Result of the transient simulation with the model IP MTJ
III.
Parameters
III.A Component Description Format (CDF)
In order to describe the parameters and the attributes of the parameters of
individual component and libraries of component, we use the Component
Description Format (CDF). It gives us the independence of from applications and
cellviews, and a graphical user interface (the Edit Component CDF form) for entering
and editing component information.
Thanks to its favorable features, we use CDF to define the initial state of IP MTJ
integrated in the write head. By entering “0” or “1” in the column “PAP” in category
“Property”, we can modify the initial state to parallel or antiparallel (see Fig.7).
Furthermore, using CDF tools we can modify multi MTJs’ states individually, which
facilitates implementation of more complex hybrid CMOS/MTJ circuits.
Fig.7 Modify the CDF parameters
If you need to define other parameters for this library, you can click Tools -> CDF ->
Edit, enter “IPRM40” as the Library Name and “celltrack”, for example, as the Cell
Name. Select “Base” as the CDF Type. Then click “Add” under Component
Parameters. (see Fig.8)
Fig.8 Edit the CDF parameters
Fill out the form as shown in Fig.8. You need to select the type of the parameter and
enter the name and defValue of the parameter. Then click “OK”.
III.B Technology Parameters
Parameter
PhiBas
Description
The Energy Barrier Height for
MgO
Vh
Voltage bias when the
TMR(real) is 1/2TMR(0)
Speed_shifting Domain wall shifting velocity
Unit
Electron-volt
Default value
0.4
Volt
0.5
m/s
100
These technology parameters depend mainly on the material composition of the
MTJ nanopillar and it is recommended to keep their default value.
III.C Device Parameters
Parameter
thick_f
c
b
tox
TMR
res_vol
Jc0
Description
Height of the Free Layer
Length
Width
Height of the Oxide Barrier
TMR(0) with Zero Volt Bias
Voltage
Voluminous resistivity
Critical current density to
place the free layer
Unit
nm
nm
nm
nm
Default value (Region)
2 (1-3)
200 (2 bits)
40
0.85 (0.6-1.2)
99% (50%-600%)
ohm/m3
A/m2
7.69e21
1e12
These device parameters depend mainly on the process and mask design and the
designers can change them to adapt their requirements.