EMPC 2005, June 12-15, Brugge, Belgium
Die-to-Wafer molecular bonding for optical interconnects and
packaging
M. Kostrzewaa, L. Di Cioccioa, J. M. Fedelia, M. Zussya, P. Regrenyb, J. C. Roussina, N.
Kerneveza
a
CEA-DRT-LETI – CEA/GRE - 17, rue des Martyrs, 38054 Grenoble cedex 9, France
b
Ecole Centrale de Lyon, LEOM, UMR CNRS 5512, 69134 Ecully cedex, France
Corresponding author: Phone: +33438782643, Fax: +33438782434, e-mail address: marek.kostrzewa@cea.fr,
Abstract
Molecular Wafer Bonding allows monolithic integration of different materials. This approach is suitable
for new applications such as Silicon On Insulator, Photonics on Silicon, advanced Systems-on-Chip and
engineering substrates. Wafer Bonding technique was initially developed to join two semiconductor wafers
together to overcome epitaxial impossibilities. Today a new technological challenge is to integrate chips of
different sizes and of different materials on one common substrate. With this target in mind, we report on
assembly of semiconductor dies on Silicon wafers (100 mm and 200 mm of diameter) for 3D packaging and
optical interconnects purpose using direct molecular bonding. The chips are diced from a bulk substrate and
bonded directly onto a silicon substrate without any organic nor metallic adhesive layer. A very thin silicon
dioxide layer is added to reinforce the adhesion. After bonding, the dies can mechanically be thinned down to 20
µm and chemically etched down to several nanometers. The dies can be of different materials, sizes and
thickness. In this paper we present especially the results on reported InP dies containing an InAsP Single
Quantum Well (SQW) for optical interconnects applications and Si, GaAs, Ge, GaN and Garnet dies bonded on
silicon for heterogeneous 3D integration and fabrication of engineered System-On-Chip.
Key words: Optical interconnects, Molecular Bonding, Advanced Packaging, 3D integration.
Introduction
The fabrication of the multifunctional
System On Chip (SOC) or Lab On Chip (LOC) is an
important challenge in the micro technology. SOC
can combine different functions and integrate
different devices like power, optical, radio frequency
and also bio-electronic devices on one substrate. The
additional functions like: micro-fluidic or micromechanical are assured by the means of MEMS
(Micro-Electro-Mechanical Systems) technology
[1]-[6]. The SOC’s have a great interest for medical,
telecommunication and automotive applications. The
functionality of this system depends on the features
and possibilities of the integration technology. The
new technologies must satisfy the actual trends in
the integrated circuits (IC) miniaturization scale.
One interesting way is to thin and bond the chips on
the substrate (die-to-wafer bonding) or to bond thins
chips one on another (die-to-die bonding). Using
theses approaches the extremely low packaging
heights [7]-[8] for 3D stacking, memories and sensor
component technology [9]-[10] can be reached.
Recently, it was also demonstrated [11][13] that the optical interconnects could decrease
power consumption and power dissipation in the IC,
could eliminate delays in the clock-signal
distribution, decrease the number of the metallic
layers and finally increase the IC features and
performances, especially in terms of maximal
operating frequency. One of possible approach is to
integrate an optical layer above CMOS Integrated
Circuit (IC). A passive waveguide structure can be
fabricated from silicon (core material) and silicon
dioxide (cladding material) independently and then a
molecular bonding can be used to assembly of
CMOS processed wafer. The next step is a
monolithic integration of III-V optical devices and
optical coupling to the passive waveguide layer.
Figure 1: Cross section of optical interconnect
configuration - over CMOS approach [14].
Figure 1 present one of possible
configuration of the optical interconnection. The
optical signal is guided from source to receiver
which converts the optical signal to the electrical
photocurrent. This current is guided by a metallic via
to the CMOS receiver which regenerates the
electrical, digital output signal. This signal can then
if necessary be distributed over a small zone by a
local electrical interconnect network [14].
Presently, the most common and most
effective approach used for integrated circuit
packaging is the flip-chip bonding which can be
used even in multilayer structure assembling [15][16]. The assembly using microsolders metallic
bumps can be useful also in the optical coupling of
photonic devices and optical waveguides [17]. This
involves the depositing of solder bumps on either
the electronic or photonic IC, then alignment and
bonding, usually using thermocompression. The
optical coupling between optical device and
waveguide can be realized thanks to micromirrors
reflecting the light from laser diode to the optical
waveguide [18]. However this technology demands
a realization and assembly of a metal coated
micromirrors before flip-chip bonding.
The use of BCB was also developed for
assembling different optical devices on silicon.
Roelkens et al. [19] demonstrated that a thin BCB
spin coated layer is optically transparent and that the
optical coupling between an optical device and
silicon dioxide waveguides can be easily realized.
However, this technique has a main inconvenient, a
BCB refractive index (n = 1.55) is slightly higher
compared to the SiO2 (n = 1.45). This implies an
intrinsic reflection at the semiconductor/polymer
interface and a reduced efficiency due to buttcoupling loss. Spin coating technique involves a
BCB deposition on a whole substrate surface. This
particularity could be harmful if we wish to integrate
dies on the circuit with MEMS or other devices on
the same substrate.
More futuristic idea concern a direct III-V
materials integration on silicon substrate. However,
the epitaxial growth of high quality III-V
heterostructures based on InP on silicon is not
possible due to lattice mismatch (8.1%). Facing to
this inconvenient, a wafer bonding could be a
promising way to obtain monolithically integrated
III-V optoelectronic devices onto the silicon.
Our recent research [20] has successfully
demonstrated hydrophilic wafer bonding and
transfer of an InP and III-V epitaxial layer stack onto
a silicon wafer at room temperature by means of
SiO2 layers on both InP and silicon substrates. This
approach allow to assembly the III-V devices
directly on silicon substrate. The thermal treatment
at 200°C guarantees a monolithic integration of both
materials.
Additionally, the molecular bonding satisfy
the requirements in term of thermal conductivity and
dissipation, transparency at the device working
wavelengths, mechanical resistance. The final choice
of the bonding technology depends on the used
materials and applications. However, for the optical
interconnects purpose, the presence of the bonding
material layer could be harmful for efficient optical
coupling.
The bonding of the singular optoelectronic
chips (dies) is more advantageous than wafer-towafer transfer because of the cost of InP or GaAs
substrates.
In this paper we present the III-V thin layer
transfer onto the silicon via a thin silicon dioxide
bonding layer and we review the adaptation of this
technique to bond the InP, GaAs, GaN, Ge, Garnet
and Si dies (from 1x1 mm² up to 3 x 3 mm²) on a
silicon substrate.
Wafer-to-Wafer Bonding Technology
The direct wafer-to-wafer molecular
bonding technology allows to achieve a good
bonding quality without any additional adhesive
materials [21]-[22].
Prior bonding silicon wafers have be flat
and uniform because the surface morphology is
critical to the quality of bonded wafers. When the
two wafers are carefully cleaned and its surfaces
hydrated thanks to chemical treatment, molecular
bonding can occur spontaneously. A complete
physical model of such a molecular bonding was
proposed and presented by Stengl et al. [23] and
Gösele et al. [24]. Bonding of oxidized silicon
wafers is also possible, however, depending of the
wafer roughness additional planarization step may
be required.
When the wafers are of dissimilar materials
one of possible way to their assembly is to deposit a
silicon oxide or a silicon nitride layer on each
surface. After being planarized and cleaned, the
surfaces are then bonded together.
The application field of the molecular
bonding is very large. M. Bruel demonstrated the
SOI (Silicon on Insulator) substrate [25] obtained by
a molecular bonding of two silicon wafers using a
‘Smart CutTM’ approach. The use of molecular
bonding technology and the implementation of
hydrogen ions allowed to prepare other advanced
substrates like: SiC on Insulator [26]-[27], GaAs on
Silicon [28]-[29] etc.
Finally, this technique which is compatible
with the requirements of semiconductor devices
fabrication allows integration of the optoelectronic
devices on the silicon wafer.
InP dies on silicon for optical interconnects.
Using a wafer-to-wafer bonding approach
we have succeed in the heterointegration of InP 50
mm wafers on silicon. For this purpose, we
thermally grow a 1 µm thick SiO2 layer on silicon
substrate which acts as a bonding layer. The Si/SiO2
wafer is polished to reach a low roughness, cleaned
in deionized water and then dried.
A 10 nm thick silicon dioxide layer is
deposited on InP (100) epi-ready substrate using
Electron Cyclotron Resonance plasma. Thanks to
this preparation, the bonding of the both InP/SiO 2
and Si/SiO2 wafers is similar to the Si/SiO2 on
Si/SiO2 bonding described above. Figure 2 presents
InP on the silicon bonding configuration. Depending
on the requirements, an epitaxial layer stack
comprising an optoelectronic devices structure can
be realized on InP substrate before oxide deposition.
InP Substrate
Sacrificial layer
Epitaxial layers
SiO2 (10 nm)
SiO2 (1 µm)
Bonding interface
Si substrate
Figure 2: InP on Silicon bonding configuration.
Such an epitaxial stack must contain also
the etch-stop layers helpful in the post-bonding
substrate removal. The molecular bonding assures a
good adhesion even at a room temperature. A
bonding energy around 200-250 mJ/m² has been
measured using the Maszara [30] blade opening
method. A thermal annealing at 200°C for 24 hours
guarantees a high bonding quality (bonding energy
EB > 700 mJ/m²). The annealing at higher
temperature is not possible because of the
differences between the thermal expansion
coefficients (TEC) of InP and Silicon. However, the
Si and InP wafers can not be debonded after
annealing at 200°C.
The bonding quality was checked by the
infrared (IR) transmission technique and confirmed
after the initial InP substrate removal using a
chloridric acid solution. The remaining etch-stop
layers can be chemically etched in order to obtain a
thin III-V layer. Using this approach we succeed in a
transfer of a 10 nm thick InP layer on Silicon. It was
demonstrated that a sophisticated technological
process like epitaxial regrowth was also possible on
the prepared thin InP layer on Silicon. [31].
The
above
wafer-to-wafer
bonding
procedure was adapted to InP dies bonding on
silicon substrate.
The dies are obtained by a mechanical
dicing of 360 µm thick InP substrate containing an
epitaxial heterostructure. The minimal die size we
have bonded is 1 x 1 mm². The pick&place
apparatus can be used to report the InP dies on the
Silicon substrate. An annealing at 200°C during
several hours reinforces adhesion between dies and
host substrate.
Mechanical dies thinning down to 20 µm is
possible after bonding without degrading the
remaining bonded material quality (Figure 3). The
additional post-bonding technological steps as
polishing may be performed. Indeed theses tests
show that the assembled InP dies on the Si substrate
can suffer from many kind of mechanical action
without debonding.
(a)
(b)
300 µm
300 µm
Figure 3: SEM image of 360 µm thick InP die
bonded on Silicon substrate (a) and of thinned
down to 20 µm die after bonding (b).
We determined the bond strength between
the die and the substrate using Die Shear testing
equipment. The obtained shear strength is of 5 MPa
 1.4 MPa for 1 mm², 360 µm thick InP dies. Theses
values are comparable to those obtained by
Neysmith and Baldwin [32] from 5 mm² silicon dies
bonded on silicon substrate using a PDMS as a
bonding layer (from 2.8 MPa to 5.5 MPa) but lower
than those bonded using a BCB as a bonding layer
(from 10.2 MPa to 12.9 MPa). However, it seems to
be sufficient for the monolithic integration of optical
devices on silicon.
When the bonded die is an epitaxial stack
including an etch-stop layer, the initial InP substrate
can be mechanically thinned down to several
micrometers and the remaining InP substrate and the
sacrificial InGaAs layer can be chemically and
selectively back-etched. Using this approach we
bonded a die containing an InAs0.65P0.35 6 nm thick
Single Quantum Well (SQW) confined between 120
nm thick InP barriers. In this case, the final thickness
of the reported die with a SQW is reduced to 256
nm.
(a)
(b)
[a.u.
]
[0.353
]
[2.569
]
[4.784
]
Figure 4: Optical image of a 256 nm thick InP die
containing an InAsP quantum well bonded on a
silicon substrate (a) and its PL cartography (b).
Figure 4 presents the photoluminescence
(PL) cartography at 1.514 µm from the reported die
after chemical back etching of the initial substrate
and etch-stop layer. The intensity is homogenous on
the whole die surface and reveal no scratch that
could be induced by mechanical thinning. The peak
intensity at 1.514 µm and the Full Width at Half
Maximum (FWHM) did not change after all the
technological process. It demonstrate that theses
technological procedures do not induce any
significant strain or stress in the reported
heterostructure which conserve its optical properties
after dies bonding.
We demonstrated also the feasibility of
direct molecular bonding of the InP dies (including
SQW) on the Silicon CMOS processed wafers (200
mm of diameter). A thick silicon dioxide layer was
deposited on CMOS structure. Polishing was then
performed to achieve required surface roughness and
CMOS wafer was cleaned. Figure 5 present the InP
dies bonded on Silicon wafer. Each die is placed on
a specific position on the CMOS wafer.
Figure 5: InP dies bonded on CMOS processed
wafer.
Using the same approach we demonstrated
direct molecular bonding of the 200 µm thick InP
dies with QW on the optical layer transferred on
CMOS processed 200 mm of diameter wafer [33].
The optical layer was composed of waveguides
processed on a SOI wafer and then transferred on a
CMOS wafer using the wafer-to-wafer bonding
process. Finally, the back side of SOI substrate was
removed and the relieved oxidized surface (SOI
buried oxide layer) was cleaned. Then, InP dies were
placed on specific spots on the CMOS wafer. Figure
6a show an optical view from an InP die bonded on
CMOS wafer with an optical layer and Figure 6b –
an in-plane view presenting the optical waveguides
transferred on CMOS wafer.
(a)
InP
requirements of advanced System On Chip
application.
We are looking for a generic technology
allowing different materials integration by a mean of
molecular bonding, that is why we bonded the dies
of Silicon (Si), Germanium (Ge), Gallium Nitride
(GaN) and Garnet using a silicon dioxide (SiO2)
layer as a bonding media and even Gallium Arsenide
(GaAs) dies bonded using a silicon nitride (Si3N4)
layer.
All the dies are separated from a bulk
material for 1-4 mm² pieces before pre-bonding
cleaning using a high precision saw with ultra-thin
diamond and resinoidal blade. Then the dies are
cleaned in the ammonia solution, rinsed, dried and
immediately bonded on oxidized silicon surface. The
bonding is reinforced by an annealing at 200°C
during several hours.
Figure 7 presents the optical views from
different dies bonded on silicon substrate (Si, GaAs,
GaN, Garnet). Figure 8 present the SEM image of a
Germanium die bonded on a silicon substrate. Note
that the Ge die was mechanically thinned down to 65
µm before SEM observation.
Actually, the dissimilar materials dies are
bonded on individual oxidized silicon substrate.
However, we are working on the integration of dies
on one common substrate. Also the evaluation of
bonding energy by a shear test is in progress.
(a)
(b)
(c)
(d)
(b)
CMOS
Figure 7: Dissimilar materials integration: (a)
2x2 mm², 525 µm thick Si; (b) 1.9x1.9 mm², 340
µm thick GaAs; (c) 2.17x2.17 mm², 337 µm thick
GaN; (d) 4.9x4.9 mm² 200 µm thick Garnet dies
bonded on silicon substrate.
Figure 6: 1.2 x 1.2 mm², 200 µm thick InP die
bonded on optical layer transferred on a CMOS
substrate (a) and optical waveguides on CMOS
(b).
The above achievements paves the way for
the introduction of optical interconnects on the intrachip level.
Dissimilar Materials Integration.
We have been studying also the feasibility
of integration of different semiconductor chips on
one common silicon substrate in order to satisfy the
Figure 8: SEM image of a 2 x 2 mm², 65 µm thick
Germanium die bonded on silicon substrate.
Concluding Remarks
In the actual stage, the full wafer InP on the
Silicon bonding is functional and can be optimized
to satisfy the needs of each application including
photonic on silicon, advanced System-On-Chip and
advanced packaging.
In this work the bonding of the individual
InP dies containing an InAsP Quantum Well was
demonstrated. The reported thin QW conserves its
optoelectronics features and performances. With
theses results in mind we can conclude that optical
devices can be integrated on the engineered optical
thin layer transferred onto CMOS wafer.
To go further, we demonstrated feasibility
of dissimilar materials integration on one common
substrate. This approach opens a new ways to
combine different functions and integrate different
devices like power, optical, radio frequency and bioelectronic devices on one platform.
Acknowledgments
This paper is a part of a study dedicated to
PICMOS project partially supported by the EU
under contract FP6-2002-IST-1-002131-PICMOS.
The authors thank the whole LTFC laboratory (LETI
– CEA – Grenoble) also Ch. Lagahe-Blanchard and
B. Aspar from TRACIT Technologies for helpful
discussions.
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