Charge Sensitive Amplifier (CSA) in cold gas of
Liquid Argon (LAr) Time Projection Chamber
(TPC)
E. BECHETOILLEa*, H. MATHEZa, and Y. ZOCCARATOa
Abstract– This paper presents our work on a 8-channel low
noise Front-End electronic coupled to a Liquid Argon (LAr) TPC
(Time Projection Chamber). Each channel consists of a Charge
Sensitive Amplifier (CSA), a band pass filter and a 50 Ohms
buffer as line driver. A serial link based on a ‘i2c-like’ protocol ,
provides multiple configuration features to the circuit by
accessing slow control registers. Only the CSA part is described
in this paper. The feedback network of the CSA is made of a
capacitance and a resistor. Their values are respectively 250 fF
and 4 MΩ. An input referred noise of, at most, 1500 e- rms must
be achieved at -100°C with an input detector capacitance of
250 pF to ensure a correct measurement of the minimal signal of
18000e- (2.88 fC). The power consumption in this cryogenic setup
must be less than 40 mW from a 3.3 V power supply.
cryogenic temperature. The main difficulties are that the
process is guaranteed and well modelled down to -40°C
whereas typical working temperatures will be around -100°C.
We designed 4 successive test-chips (Fig 1) tested in liquid
nitrogen in order to study and optimize the overall noise
performance and transient response of this front end
architecture.
I. INTRODUCTION
We developed an integrated circuit for the readout of LAr
TPC neutrino detectors [1]. These detectors employ LAr
simultaneously as massive target and detection medium. The
detection of secondary particles produced in neutrino
interactions is achieved by collecting, on a system of wires at
the sides of the detector, the electric charges from the
ionization losses. Two planar coordinates are measured by the
wires geometry, the third, orthogonal, coordinate is obtained
by measuring the drift time. Typical signals are 3 fC per
particle per wire but they can reach up to 120 fC. In order to
limit input cable capacitances and therefore the noise, we
designed a front end electronics to be installed as close as
possible to the wires. The ASIC will be installed above the
liquid argon level and it will be operating at the temperatures
of the argon vapours contained in the upper part of the
cryostat. Depending on the height above the liquid level, the
electronic boards will be at a temperature ranging between 150°C and -100°C. The circuit should dissipate as little heat as
possible to prevent additional warming of the detector. We
have selected a low cost standard 0.35 μm CMOS technology
from AMS (Austria-MicroSystems) for its high performance in
analog design. Such CMOS process also works well at
a
IPNL, University of Lyon, CNRS/IN2P3, MICRHAU,
4 rue E. Fermi 69622 Villeurbanne, France
E-mail: e.bechetoille@ipnl.in2p3.fr.
Version 1 : PA_TOP Version 2 : TOP_EST
1654µm X 1664µm= 1974µm X 2364µm
2.75mm²
=4.66mm²
Version 3 : TOPPING
1914µm X 2544µm
=4.88mm²
Version 4 : T2K_V4
1914µm X 2684µm=5.14mm²
Fig. 1. Four chips die photography
Detector
Charge Sensitive Amplifier
shaper
-A
buffer
H
Cpa
CD
250pF
Rpa
Ho  p
H ( p) 
(1    p) 2
τ= [0.5; 1; 2 ;4]µs
Input current
500ns
CSA output
Shaper output
500ns
500ns
Fig.2. One channel block schematic
The block schematic of one of the channels is drawn on
fig 2. The CSA has to integrate a charge equivalent to
18000 electrons collected over 500 ns, in presence of an input
capacitance of 250 pF. The input referred noise has to be as
low as 1500 electrons in order to achieve a signal to noise ratio
of at least 12, optimized by the shaper. The buffer drives the
line bringing the signals outside the cryostat. A readout system
[3] based on µTCA frame is used in conjunction with our
setup in order to acquire and process the signal.
II. CSA DESCRIPTION
The CSA consists of a folded cascode amplifier (fig 3). The
bias voltage of the cascode transistor is tuned by the Gain
Boost technique illustrated in [2] to increase the gain
bandwidth product. The closed loop stability is obtained with
the feedforward technique detailed in [3]. The bandwidth is
determined by the dominant pole, given by:
g
(1)
f c  dsTcasc
2C out
where Cout is the capacitance at the node on the gate of the
output source follower. Feedforward technique is implemented
by adding passive components RZ and CZ. Rz is chosen to
satisfy the following condition:
1
(2)
g dsT 1 
 g mTcasc
Rz
and Cz is optimized for a good phase margin. The choice of the
added component allows second-pole cancellation and must be
chosen very carefully.
In order to minimize the error of charge collection into the
feedback capacitor Cf, the DC gain of the amplifier (A0) needs
to be high enough to verify the equation CD << A0.Cf , which
means A0 >> 250 pF/250 fF. A minimum of 93 dB DC gain is
needed to acquire 98% of the input charges.
As the TPC to be coupled to the CSA has a very large
capacitance, large size mosfet are employed, especially for the
input transistor (W/L = 8100 µm/0.35µm) to reduce its
channel thermal noise. Its simulated bias current is 14 mA at 100°C and the transconductance reaches up to 277 mA/V.
Table 1 summarize the operating bias current and the small
signal parameters of the 3 main transistors of this amplifier.
The input transistor was implemented with large gate width W
and minimal gate length L (0.35 mm) in order to achieve high
W/L ratio (for large gm) while optimizing WL product (for
reducing the input capacitance). We tried to stick to the
optimum gate width and noise optimization, W was performed
as recommended by Moser, and Radeka [5-6] according to
equation (1).
1
(3)
Cd  C f 
W 
2Cox Lmin
However in our case the first limitation encountered was
due to the parasitic capacitances of the integrated large
feedback resistor Rf = 4MΩ. Such parasitic capacitances were
significant comparing to the feedback capacitance Cf = 250fF.
As a consequence, the overall conversion gain is made in two
steps, first with the CSA and the minimal acceptable value for
Cf, and a second gain stage of 4 with the CR-RC shaper.
Several feedback networks can be used by switching the
passives components Rf1-Rf4 and Cf1-Cf2 trough I2C serial
interface.
Fig.3. CSA schematic
On Fig.3, the values of resistance and capacitances are as
follows.
Rf1=Rf2=Rf3=Rf4=1MΩ;
Cf1=Cf2=250fF;
Rz=300Ω and Cz=1pF. The detector capacitance is estimated
at 250pF and the AC coupling capacitance Cc is equal to
100nF. The current that flows into the input transistor T1 is
IDT1=I1-Icasc. See Table 1 for the consumption of each
element.
Temp
IDT1
(mA)
gmT1
(mA)
IDTcasc
(µA)
gmTcasc
(mA/V)
IDsf
(µA)
25°C
9.3
11.8
12.5
14.1
124
180
204
280
116
109
107
103
92
83
81
75
235
223
220
211
-75°C
-100°C
-150°C
Power
(mW)
34.9
42.8
45.0
50.0
Table 1 : small signal parameters and operating bias current
III. NOISE ANALYSIS
This noise analysis is simplified and reduced to the input
transistor channel thermal noise. Specific noise calculation is
well described by Nygard et al [7]. Otherwise, the input
transistor is bias to operate in strong inversion region. The
optimization is based on the EKV model and the inversion
coefficient IC [8] is a relevant parameter to identify the
operating region and the level of inversion of input MOS
transistor. The inversion coefficient is defined as:
ID
W
(4)
IC 
,   Cox
2
2 n U t
L
where ID is the drain current, Ut the thermal voltage, n the
slope factor, Cox the oxyde capacitance, W/L the geometry
ratio of the transistor and µ the mobility of carriers in the
transistor channel.
In this design  reached up to 1.4 A/V2. The drain current is
a function of temperature, 9.4 mA at 25°C and 14 mA at 100°C due to bias current variation, and the slope factor close
to 1.2. As a result, the inversion coefficient is respectively 5
and 26 which indicates that the input transistor is biased in
strong inversion region.
In front end design using a CSA followed by a CR-RC filter,
the final Equivalent Noise Charge (ENC) referred to the input
in electrons can be expressed as (5).
ENC 
eCd
q
kT
3 s g m
(5)
where e the neper number, Cd the detector capacitance, s is
the shaping time constant, k the Boltzmann constant, T the
temperature, gm the input transistor transconductance,
For simplicity only one term is taken in account which
corresponds to the thermal noise of the input transistor’s
channel. Other contributors such as feedback resistor thermal
noise source and parallel input noise current (shot-noise
related to the input transistor’s gate leakage current) can be
neglected and so do not appear in (3). In this design, the noise
due to the input transistor is 30% of the overall noise.
According to (3), the noise is dominated by the value of gm
and thus by the bias current ID, the geometry ratio W/L of the
transistor, the slope factor n and the mobility µ of carriers in
the transistor channel (6).
gm 
2 I D
n
(6)
ENC 
1 N noise
*
q Gconv
(8)
The electronic output voltage noise Vnoise contribution was
measured as a function of detector capacitance and
temperature. Two measurements were made (with ASIC and
without ASIC) in order to remove the board and test bench
noise. Noise result and Gconv as a function of temperature is
plotted on fig 4.
2000
20
18.9
18.6
18.1
1915
1799
1800
18
16
14.0
14
1600
1584
1524
1400
-200
AVERAGE ENC (e-)
Gconv (mV/fC)
12
10
-150
-100
-50
0
50
Fig.4. ENC and Gconv as a function of temperature
Mobility (7) is a strong function of temperature and
depending on the doping level approximately given by:
g m  T 
(7)
In (5), a standard value of  is 1.5 for low doping level. At a
given bias current of the input transistor, gm will increase as
the temperature decreases, which is the case in this cryogenic
design. For a temperature variation from 25°C to -100°C, the
mobility can increase by a factor from 4 to 6. As a result g m
increase and low noise performance can be achieved.
According to the previous equation a decrease of 20% on ENC
would be expected. However, the overall ENC reduction is
lower (see next paragraph), since other noise contributions
evolves differently.
It should also be noted that very large gm of the input
transistor leaves noise contribution of the input serial polygate
resistance rpoly more significant and non-negligible. A special
care has been taken in account during the layout design.
IV. TESTING RESULTS
Noise performance is a key issue in front-end design. The
aim of 1500 e- ENC while expecting a signal of 18 000 e-, had
to be reached for a temperature of -100°C. The overall test
chain was calibrated with a very low-pulse charge injection
(20 fC) to determine its charge gain Gconv (14 mV/fC). The
ENC in electrons was calculated from the output noise of the
test chain with (6):
The noise reduction due to the increase of mobility is 17%
from room temperature to the nominal one (-100°C). At lower
temperature some oscillations occurs so the ENC can not be
measured properly. It can be seen as a drastic increase of noise
but not correspond to a noisy ASIC.
In the simplified equation (3) the output noise is a linear
function of the detector capacitance. These measurements were
done for the 4 versions of ASIC at different temperature (fig
5). The best results is obtained with the version 1 (V1) but the
shaper was external and the amplifier gain band width product
lower. The noise was 1200 electrons at -100°C (not showed on
this plot). The excess noise for version 3 (V3) is due to a
layout problem on a resistor which determine the close loop
stability of the amplifier. The induce oscillation can be seen as
an increase of noise.
The last version (V4) which is close to the final one works
well down to -100°C (fig4). Measurements were done for
several detector capacitors at room temperature and at -75°C.
The noise reduction is 17% for a detector capacitance of
250 pF. Noise performance of ENC = 874 e- + 3.73 e/pF has
been achieved.
ACKNOWLEDGMENT
This work was done in the context of the T2K collaboration
and the R&D programmes on giant TPC detectors devoted to
the study of neutrino physics and astro-particle physics. We
thank our colleagues from the IPN Lyon Neutrino group for
having stimulated and supported this development.
REFERENCES
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Fig.5. ENC as a function of temperature
The dotted line on fig 5 is the ENC calculated from eq 5 for
comparison. It has been taken in account that the noise due to the
input transistor contribute at the level of 30% of the overall
noise.
[3]
[4]
[5]
[6]
V. CONCLUSION
Using a standard CMOS process we designed and optimized
a low noise charge sensitive amplifier to be used for the
readout of liquid argon TPCs, which are characterized by large
detector capacitance. This technology was not characterized
for so low temperatures so we made successive iterations on
test-chips in order to achieve an equivalent noise of 1500
electrons RMS, power dissipation less than 40 mW and stable
performances.
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