On The Forefront: September, 1997
by Phil Zarrow
OSPs – Better Living Through Modern Chemistry
OSPs – Myths and Legends
As discussed in an earlier column, Organic Solderability Protectants (OSPs) have
gained a great deal of popularity and usage. For many applications the Hot Air Solder
Leveling (HASL) process has reached its limit. Very thin substrates, such as those found
in PCMCIA assemblies as well as flex circuitry do not usually fare well when immersed
in a pool of molten solder (unless the objective is a substrate that resembles a potato
chip). Solder coatings on circuit boards such as those produced through the Hot Air
Solder Leveling process are difficult to tightly control in terms of thickness and thus
affect the coplanarity of the substrate surface. This becomes important when dealing
with fine-pitch devices, Chip-Scale packages and flip-chip direct chip attach. Circuit
boards processed with Organic Solderability Protectants offer a solution to both of these
problems.
OSPs are typically azole based organic films. Hence, the coatings are lead-free
and are very planar. OSPs decompose at elevated temperatures such as those experienced
during the wave and reflow soldering processes.
The copper-clad PCB substrates are fabricated using the subtractive method,
however, they are not solder coated. The bare copper is coated, instead, with an organic
sealant, which insulates the copper from exposure to the air and, hence, prevents
oxidation. OSPs are placed directly over the bare copper pads and traces on the outer
layers of the printed circuit board. The thin, consistent layer allows for tight control in
the Z-axis, preventing opens due to coplanarity tolerances.
The PCB assemblies are assembled in the usual manner with solder paste
stenciled on and components placed onto the substrate. The PCBs are then reflow
soldered and/or wave-soldered. Exposed to both flux and heat, the OSP vaporizes from
the surface being soldered during the Preheat phase of the reflow process leaving the
solder paste in direct contact with the copper pads. On double sided assemblies, the
second side remains “sealed” (through the thermal excursion of soldering the topside) as
there is no flux present to react with the OSP. Of course, when the second side is
soldered, the flux presented by the solder paste reflow, the spray fluxer (wavesoldering)
or the flux (hand soldering) works with the heat to allow successful soldering.
The current generation of OSPs, unlike the earlier versions do not require nitrogen
atmospheres for reflow or wave soldering. Tests by many users have indicated that the
OSPs can survive multiple thermal excursions, even with fairly long storage times in
between. Most are compatible with no-clean flux formulations.
However, what about bonding situations in which flux is not present such as wire
bonding? After all, the OSP is a coating over the entire substrate surface, including the
metallized surfaces. There are a number of us doing chip-on-board and, as attractive as
flip-chip is, there is not an overabundance of die available in this configuration yet. Well,
it is possible to wire bond to an OSP-treated circuit board.
Brian Greig of SCI was faced with this challenge some time ago. SCI had been
assembling chip-on-flex with aluminum wedge bonding to a selective Ni/Au
electroplated surface. The quest for higher yields through incorporation of OSPs led to
an investigation as to the compatibility between the two processes.
Brian’s test vehicle was comprised of three flex substrates. One was uncoated,
one was coated with 0.35 microns of a leading OSP formulation and one was coated to
0.50 microns of the same OSP. The coated substrates thus represented the nominal and
maximum OSP thicknesses that are typically found in the industry. Interestingly, the
actual coating over the gold die attach and bonding areas work out to a thickness of
approximately one-tenth to one-twentieth of that thickness.
After performing the wire bond operation, pull tests were performed to evaluate
the strength of the bonds. A portion of the samples were baked (150 degrees C for 8
hours) to accelerate any wire bond interface problems. Brian found that the average pull
strength declined about 2 grams with the standard deviation tightening up as a result of
the bake thus indicating no appreciable interference by the OSP to the formation of a
solid metallurgical bond. There were a number of mode 5 destruct failures (2nd bond lifts
from the substrate) on the OSP-coated substrates prior to baking. However, though the
OSP coating interfered to a certain degree with bond formation, the actual impact on pull
strength was relatively insignificant. After baking the substrates, this particular failure
mode shift effectively disappeared. In addition, Brain reports that the customer has seen
no electrical or mechanical test failures, which could be attributed to the use of the
coating and has hence, qualified it. All in all, they have found that SMT yields are
significantly better using the OSP coating.
Getting It On
Now that we have further established the viability and versatility of OSPs, there
seems to be a bit of a debate as to what is the best way to apply an OSP. In practice, the
printed circuit fabrication house typically employs one of two methods. The coating can
either be applied via immersion (or dipping the substrate into a reservoir of the material)
or by means of a conveyorized spray process. Advocates of the spray process claim that
dipping is “low tech” and can only result in uneven coating thickness. The immersion
supporters claim that spraying results in clogged nozzles, inappropriate aeration of the
chemistry, and uneven spray patterns.
The reality appears that either process can work. A timer/control system can
regulate exposure chemical exposure times in an immersion process thus yielding
repeatable results. The chemistry, for the most part, is “non-directional” and a full
immersion produces a fairly uniform reaction across all substrate surfaces. Spraying is
also a very good process and, with proper regulation, the unpleasantness mentioned is
easily avoidable. Conveyorized spray systems also may be the optimum way to handle
small substrates. Thus, either type of processing will work well when properly setup and
controlled. Where have we heard that benediction before?
As predicted in this column a few months ago, ultra-low residue no-clean solder
pastes that do not require reflow in an inert (nitrogen) atmosphere have arrived. Such a
prediction was no great feat as the pursuit of a solder paste to be so versatile in terms of
function and process requirements has been in place since the late 1980’s. In any event,
such solder pastes, such as Alpha’s Ultraprint 78 are here.
In a no-clean we are looking three main characteristics. We want the residue to
be non-volatile in that it can be left on the circuit board assembly somewhat indefinitely
or at least for the reliability life of the application. We want it cosmetically appealing in
that the residue present is relatively invisible. This is important if the circuit board
assembly will be seen by the end-user and less so if it is not. Finally, if the assembly is to
be tested via a bed-of-nails fixture, the mainstay of in-circuit testing, the residue must be
testable reliably and repeatably.
The later has been a tough nut to crack. Even solder pastes with very low solids
content, the test probes either couldn’t penetrate the residue reliably or the residue would
eventually “gum” up the probes. Both tendencies result in false reading which pretty
much defeats the purpose of testing or, at the very least, certainly takes the fun out of it.
Achieving all this is not easy. While it is a matter of reducing the solids content
of the flux, these solids contain activators and other chemistries that define the workings
of the paste. For example, such a reduction, while yielding a residue that is both
transparent and testable, may also result in a less aggressive fluxing action. Thus the
aforementioned requirement that the reflow soldering operation to take place in a
somewhat inert atmosphere to prevent further oxidation catalyzed by the thermal
excursion of the process. Or the rheology of the paste is altered to the degree that the
tendency to slump is amplified. Or the tack time of the wet solder paste is drastically
reduced. Or all of the above.
So, the development of no-clean solder pastes whose solids content is so low that
it is truly testable and cosmetically acceptable yet have working process parameters that
are undemanding is a major milestone for the industry. If you are planning a no-clean
solder paste evaluation in the near future, this new formulation from Alpha, as well as
others that will be, no doubt forthcoming from other manufacturers, should definitely be
among the candidates.
Special thanks to Brian Greig of SCI, Huntsville, Alabama for sharing his study.
Phil Zarrow is a surface-mount process consultant and president of ITM, Inc.,
Durham, NH, e-mail: ITM@itm-smt.com