ANALYSIS WITH HIGH SPEED MULTI-OUTPUT 256-BIT
CARRY LOOK-AHEAD ADDERS OF 32NM USING
DOMINO LOGIC
A.Bharathi1, M.Manikandan2, K.Rajasri3
Abstract—This paper presents the carry look-ahead
adder algorithm with high speed, less area consuming less
power is being analyzed and compared with different
technologies of L=32nm.In adder circuit delay is the
major drawback. To overcome this domino logic is used
to minimize the circuit and reduce the number of
transistors size for 256-bit CLA adder using HSPICE
simulation tool. For higher speed of the domino circuit in
CMOS technology Manchester carry chain adder(MCC)
is proposed.
Index Terms— Addition, Carry-Look ahead Adder
(CLA), High Performance, domino logic, CMOS
technology, HSPICE TOOL
1.INTRODUCTION
ADDITION is the most commonly used in arithmetic operation and
also the speed-limiting element to make faster VLSI processors. The
objective of Computer Arithmetic is to develop appropriate
algorithms that are utilizing available hardware in the most efficient
way. Ultimately, speed, power and chip area are the most often used
measures, making a strong link between the algorithms and
technology of implementation. Dynamic gates are faster than static
gates despite the extra fet in the pull down path because of the
reduction in self-loading and the limitation of the pull up
short-circuit current during the first part of the output transition.
Dynamic gates cannot be cascaded. In integrated circuit design,
dynamic logic is a design methodology in combinatory logic
circuits, particularly those implemented in MOS technology. It is
distinguished from the so-called static logic by exploiting temporary
storage of information in stray and gate capacitances. It was popular
in a recent resurgence in the design of high speed digital electronics,
particularly computer CPUs. Dynamic logic circuits are usually
faster than static counterparts, and require less surface area, but are
more difficult to design. Dynamic logic has a higher toggle rate than
static logic but the capacitive loads are smaller so the overall power
consumption of dynamic logic may be higher or lower depending on
various tradeoffs.
In the most common version of this concept, the output is driven
high or low during distinct parts of the clock cycle. In contrast, in
dynamic logic, there is not always a mechanism driving the output
high or low. During the time intervals when the output is not being
actively driven, its impedance causes it to maintain a level within
some tolerance range of the driven level.
In a basic design, to start waiting, the CPU would write to a register
to set a binary latch bit which would be ANDed or ORed with the
processor clock, stopping the processor. A signal from a peripheral
device would reset this latch, resuming CPU operation. The
hardware logic must gate the latch control inputs as necessary to
ensure that a latch output transition does not cause the clock signal
level to instantaneously change and cause a clock pulse, either high
or low, that is shorter than normal. Dynamic logic, when properly
designed, can be over twice as fast as static logic. It uses only the
faster N transistors, which improve transistor sizing optimizations.
Static logic is slower because it has twice the capacitive loading,
higher thresholds, and uses slow P transistors for logic
2.RELATED WORK
Dynamic logic can be harder to work with, but it may be the only
choice when increased processing speed is needed. Most electronics
running at over 2 GHz these days require the use of dynamic,
although some manufacturers such as Intel have completely
switched to static logic to reduce power consumption. Note that
reducing power use not only extends the running time with limited
power sources such as batteries ,but it also reduces the thermal
design requirements, reducing the size of needed heat sinks, fans,
etc., which in turn reduces system weight and cost.
In this paper presents the carry look-ahead adders in domino
circuits for faster requirement of the VLSI processors or digital
signal processors. The Manchester carry chain adder (MCC) is the
most popular dynamic (domino) CLA, is proposed with an
implementation in VLSI. The MCC have enabled the development
of multi-output domino gates which have given area and speed
improvement with respect to single output. The efficiency of the
MCC is trying to transfer its structure to static logic. In a report has
been made of dynamic CMOS 4-bit CLA adder in multi-output logic
which reduces the number of transistors which considered to a
conventional schema. However, the simulation results shown any
speed improvement but reduce delay is been analyzed and compared
with different technologies having an supply voltage of VDD=1.2V
and 1V is defined.
The performance of the domino logic circuits of an 256-bit CLA
adder has the generate and propagate signal of AND or XOR gates.
When CLK is low, dynamic node is precharged high and buffer
inverter output is low. NMOS in the next logic block will be off.
When CLK goes high, dynamic node is conditionally discharged
and the buffer output will conditionally go high. Since discharge can
only happen once, buffer output can only make one low-to-high
transition. When domino gates are cascaded, as each gate evaluates,
if its output rises, it will trigger the evaluation of the next stage, and
1
so on… like a line of dominos falling. Like dominos, once the
internal node in a gate falls, it stays fallen until it is “picked up” by
the precharge phase of the next cycle. Thus many gates may evaluate
in one eval cycle. charge sharing between nodes in the pull down
network and the dynamic node can unintentionally reduce the
voltage of the dynamic node enough to switch output buffer .The
addition of the output inverter makes domino gates non-inverting.
One can often design around this limitation, but some circuits
cannot be implemented solely using Domino logic unless both
polarities (true and complement) of the inputs are available. If both
polarities of inputs are available then we can generate both polarities
of internal signals with two domino gates so subsequent stages will
have both polarities of their inputs available.
C1=G0+P0.C0
C2=G1+G0.P1+C0.P0.P1
C3=G2+G1.P2+G0.P1.P2+C0.P0.P1.P2
C4=G3+G2.P3+G1.P2.P3+G0.P1.P2.P3+C0.P0.P1.P2
To determine whether a bit pair will generate a carry, the following
logic works:
Gi=Ai.Bi
1.1 CIRCUIT DESIGN
Since domino gate outputs are low during the precharge phase, gates
which have only domino output nodes as inputs don’t need the
evaluate nfet since all the nfets in the pull down will be off anyway.
if evaluate nfet is removed, precharge will ripple through
cascaded gates just like evaluates. Maybe only remove for gates
where nfet stack is tall (i.e. resistive) enough that pull up will satisfy
anyway before ripple reaches gates and turns off pull downs. To
avoid short-circuit current, delay arrival of precharge signal to
downstream gate.
Fig 2 layout diagrams for generate AND signal
Fig.1 schematic diagram of generate AND signal
Figure 1 shows the implementation of generate signal in domino
logic. The circuit will possesses generally two state precharge state
and evaluation state. If the clock signal goes to value ‘0’, then the
circuit will enter into precharge state and PMOS will get connected
to ground and output will maintain the value of 0. If the clock makes
the transition from 0 to 1 then the circuit will enter into evaluation
state and the output depends on the input value. Since generate
signal possess AND operation if both input are maintained at 1, 1
then the output gi will be maintained at 1 else the output value will
be maintained at 0 i.e gi=0.
For the example provided, from the preliminary basics the logic
for the generate (g) and propagate (p) values are given below. Note
Fig.3 schematic diagram of propagate or signal
Fig.3 shows When CLK is low, evaluate nfet is off and precharge
PMOS is on output node is precharged to VDD, other nodes may
precharge to VDD - Vth, depending on values of inputs .When CLK
goes, high evaluate nfet is on and precharge PMOS is off output
node may be discharged if inputs have configured a conducting path
to GND, otherwise output node stays charged high. inputs must be
stable before CLK goes high because once output has been
discharged it won’t go high again until next cycle for same reason,
noise/glitches on inputs cannot exceed nfet threshold, a much more
stringent requirement than for static CMOS gates.
that the numeric value determines the signal from the circuit above,
starting from 0 on the far left to 3 on the far right:
C1=G0+P0 .C0
C2=G1+P1 .C1
C3=G2+P2 .C2
C4=G3+P3 .C3
Substituting C1 into C2, then C2 into C3, then C3 into C4 yields the
To determine whether a bit pair will propagate a carry, either of the
following logic statements work:
Pi=Ai xor Bi
Pi=Ai +Bi
expanded equations
2
The layout diagram has been drawn using microwind tool has
shown below
Technique
90nm
65nm
32nm
Static
2.7096
2.3285
2.0125
Dynamic
1.9969
1.9022
1.0624
Table1: comparisons with technology and sum delay
Technique
90nm
65nm
32nm
Static
2.6421
2.2405
2.0120
Dynamic
1.9033
1.9022
1.0756
Table2: comparisons with technology and carry delay
Fig.4 layout diagram for propagate XOR signal
In this paper mainly focus on reducing delay when temperature
increases from 25oc to 70 oc. when the temperature increases power
dissipation will occur, it may be a static power or dynamic power.
so, power consumed for the circuit in the system is less. The system
performance gets reduced accordingly.
2. PROPOSED WORK
The Manchester Carry-Chain Adder is a chain of pass-transistors
that are used to implement the carry chain. During precharge, all
intermediate nodes (e.g. Cout0) are charged to Vdd. During the
evaluation phase, Cout_k is discharged if there is an incoming carry
Cin0 and the previous propagate signals (P 0...Pk-1) are high. Only 4
diffusion capacitances are present at each node, but the distributed
RC-nature of the chain results in a delay that is quadratic with the
number of bits. Transistor sizing was performed to improve
performance. The details are elaborated on in the design strategy
section. The Manchester carry chain was designed using dynamic
logic and implements the following logical function:
Coi=Gi+PiCoi−1
Fig 5 schematic diagram of votage vs temperature
In this paper three types of technologies with an adders circuit are
presented with L=0.12μm technology and with a supply voltage of
1.2V. These high performance domino styles improve the scalability
of multiple bit domino logic adders. Using these methods it is
possible to implement the adder circuits with a transistor gate length
of L=22nm along with a supply voltage of 0.8V. These adder
circuits are superior in performance compared to conventional static
logic adders. These adder circuits minimize the chip area, minimize
the leakage power, and improve the noise tolerance without much
speed degradation. Also the delay between the gates is now reduced
to the order of pico seconds. These types of domino logic circuits
can be used in high performance microprocessors.
By considering this below, comparing these technologies with static
and dynamic(domino) gates
Delay in Nano seconds
Fig.6 4bit Manchester carry chain adder
Manchester carry chain adder presents a efficient implementation of
multi-output domino CMOS logic. The further work has been
analyzed with different technologies and results are observed using
HSPICE tool.
3. SIMULATION RESULTS
3
The simulations were performed using L=0.12μm technology along
with the supply voltage VDD=1.2V. In this paper a 256-bit adder is
constructed using three different domino technologies such as
90nm,65nm,22nm .This adder circuit has the area overhead of an
extra NMOS transistor which is connected to the keeper from the
dynamic(domino) circuit. This adder circuit has much better noise
margin, low leakage current and low power consumption compared
to the adder circuits designed L=32nm using domino logic styles
with traditional feedback keepers. The adder circuit designed using
carry look-ahead adder domino logic is used but it consumes some
additional power due to the transistors count has been increased.
The following simulation result is
Fig 9 Power analysis graph
Fig.7 simulation diagram of voltage vs time
BITS/DELAY
SUM
DELAY(ns)
CARRY
DELAY(ns)
POWER(uw)
4BIT
247
242
37
8BIT
335
320
39
16BIT
355
340
42
32BIT
425
415
45
64BIT
545
520
51
128BIT
612
595
65
256BIT
705
687
73
Table.3 comparison of sum delay,carry delay,and power
4. CONCLUSION
In this paper the performance of 256-bit adder circuit designed using
in dynamic (domino) circuit techniques is analyzed in detail and its
performance is compared with static adder circuits. The 256-bit
adder circuit is simulated using L=32 nm technology along with
supply voltage VDD=0.8V. The experimental results shows that
these adder circuits gives superior performance compared to adder
circuits designed using conventional domino techniques. Further,
Manchester carry chain adder in 256-bit is used for increasing high
speed and reduced delay in the domino circuit.
Fig .8 comparison of temperature vs sum ,carry, power graph
The delay graph is plotted with rest to number of bits and
the gate length is 32nm technology. In this graph explain the
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