Bus
A bus is a collection of wires used to connect different devices within a computing system. Most of the
internal system components, including the processor, cache, memory, expansion cards and storage
devices, talk to each other over one or more buses.
This GPS system needs a backplane bus to connect the various modules, with interfaces for the CPU,
screen display, user keypad, network adapter (satellite receiver and transmitter), device memory and a
user plug-in port, the best being a USB port for a cars computer, flash drive or printer. There will also
be various local buses within modules, e.g. for all devices connected to the DMA controller, processors
and main memory, and within the controllers for the user ports and network adapter.
There are many standards for buses. One is the Industry Standard Architecture (ISA) bus, which is a
backplane bus introduced by Intell in 1984. This is still widely used but has become a bottleneck for
performance speeds. Plug and Play (PnP) designed to enable simple and robust connectivity among
stand-alone devices and PCs from many different vendors. EISA Bus (Extended Industry Standard
Architecture) originated in 1988 & 1989 received limited use in 386 and 486 based PCs before being
made obsolete by the PCI bus. Also, Multibus standard was originally developed by Intel. It specified
four busses and was adopted as IEEE 796. Multibus is popular in industrial systems, and while it is a
fairly old bus, it is still in common use. In addition, the STD 32® Bus combines a small, industrial
strength architecture with the functionality and performance of today's high-end personal computers. It
is a 32-bit scalable computer catering for demanding real-time control and data acquisition applications
where system size and cost are important priorities9. These are a few of the many ‘standards’ available.
Current Technology
The Intel PXA255 has a fast internal system bus which operates at 200MHz between components and
400MHz at the core. This can be extended from the interfaces at the processor ports to the peripherals
directly as 32 bit parallel buses. This 32 bit network will be the backplane bus for the GPS system.
For local buses, there are shared and switched buses, commonly used within and between CPU chips.
The shared bus is still the most common way to move on-chip data. In this scheme, a large multiplexer
drives a single interconnect net which selects the source, but sends the signals to all devices on the net
(within the CPU). In 2002, MIPS Technologies introduced the IP switch bus that uses multi-layer
capabilities (common on networks) to allow two simultaneous transfers on the same clock cycle.
Switched buses are overtaking shared buses due to increasing industry demands for bandwidth and
latency. These would improve bandwidth and reduce latency in handling data streams within the GPS
system CPU7.
Future Technology
Compaq, HP, and IBM are working hard on Future I/O, which is based on a point-to-point, switchedfabric interconnect. The initial throughput from Future I/O connections will be 1Gbyte/sec per link in
either direction. Work on Future I/O, which is still in the specification stage, should result in one
interconnect that can be used for communication among processors in a cluster, as well as for
technologies that need the additional bandwidth, such as Fibre Channel, SCSI, and Gigabit Ethernet.
Hitachi, NEC, Siemens, and Sun Microsystems have thrown their support behind a new bus
architecture dubbed Next Generation I/O, or NGIO. Much like Future I/O, NGIO is based on a
switched-fabric architecture. NGIO's Physical layer is very much like Fibre Channel's, which supports
speeds of 1.25Gbits/sec or 2.5Gbits/sec.10
Versa Module Eurocard (VME) bus continues to be a favorable choice as an industrial embedded
computing architecture. The VME technology family of specifications has grown significantly since its
inception. VMEbus has expanded from the original core of a parallel VME32 specification, a VME
Subsystem bus, and a VME serial interconnect to the broad family of complementary state-of-the art
specifications that have been ratified through 2004. VMEbus International Trade Association (VITA)
VITA 41 -- VME Switched Serial (VXS) combines the existing event-driven parallel VMEbus with
enhancements to support switch fabrics. Several fabric protocols are mapped out for VXS including, 10
Gigabit Ethernet, PCI Express, Serial RapidIO and Infiniband. VME's parallel bus architecture
provides bus control and maintenance data, handling everything from single byte transactions to
300+MB/s block data transfers11.
Recommendations
For both local and backplane buses, I2C can be used. I2C devices have switched buses. Fast-mode is
added. This allows a fourfold increase of the bit rate up to 400 kbit/s. Fast-mode devices are
downwards compatible i.e. they can be used in a 0 to 100 kbit/s I2C-bus system. 10-bit addressing is
added. This allows 1024 additional slave addresses. Slope control and input filtering for Fast-mode
devices is specified to improve the EMC behaviour like noise8. The PXA255 can connect to multiple
32bit buses (200MHz). These will in turn act as backplane buses for the peripheral devices. PCMCIA
device controller for the screen, microphone and speaker is on board the processor. There are also 17
dedicated I/O ports for extra user devices, so the buses (from the processor) shall connect to a
Bluetooth, USB, serial and headphone multi-port device.
Circuit plan
Microphone
LCD
Screen
32bit
200MHz
parallel bus
Multiport
Internal Bus
Multiport
device
BlueTooth
Transceiver
PXA355
Processor
Satellite
Transceiver
Appendix
CPU:
USB:
DMA:
IC:
I2C:
Central Processing Unit
Universal Serial Bus
Direct Memory Access
A computer feature that allows peripheral systems to access the memory for both read and
write operations without affecting the state of the computer's central processor.
www.crucial.com/uk/library/glossary.asp
Integrated Circuit
Inter-IC bus
I2C is a bi-directional two wire bus that was developed by Philips for use in their televisions
in the 1980s. Today, I2C is used in all types of embedded systems.
http://www.totalphase.com/docs/i2c/
References
1. Jennifer Brown. Computer Dealer News. Willowdale: Jul 14, 2000.Vol.16, Iss. 14; pg. 48, 1 pgs
2. Gibbs, Mark. Network World Canada. Downsview: Sep 17, 2004.Vol.14, Iss. 17; pg. 23
3. Sean McKee. Computer Dealer News. Willowdale: Feb 11, 2000.Vol.16, Iss. 3; pg. 34, 1 pgs
4. Dave Bursky. Electronic Design. Cleveland: Mar 17, 2005.Vol.53, Iss. 6; pg. 34, 1 pgs
5. 2005 Intel Corporation, Overview of PXA255 processor
http://www.intel.com/design/pca/prodbref/252780.htm
6. Copyright © 2002 MIPS Technologies, Inc. SOC-it TM System Controller
http://www.mips.com/content/PressRoom/PressKits/files/SOC-it_Press_Presentation.pdf
7. TechOnLine Publication Date: Sep. 24, 2002
http://www.techonline.com/community/ed_resource/feature_article/21224
8. Sealig Inc IC Technology: 2002
http://www.saelig.com/calibre.htm
9. PC Guide Magazine
http://www.pcguide.com/ref/mbsys/buses/
10. Note: written by Anita Karve, was originally published in Network Magazine.
http://www.networkmagazine.com/shared/article/showArticle.jhtml?articleId=8702415&classroom
=
11. Nov. 12, 2004 Whitepaper from the VMEbus International Trade Association (VITA)
http://www.deviceforge.com/articles/AT7436295498.html