EE466 VLSI Design
Term Project
Option 1
Due: Dec. 18, 2008
1. Objective: Design a pipelined memory system.
This project should give you insight into the design of a digital system, pipelining, timing
issues, system performance, system layout, and system level testing.
2. Tasks:
Due: Nov. 14, 2008
Points: 15
Perform a top-down design of a pipelined memory system by providing a block diagram
of the system and its timing sequence. Design a 16 × 16-bit pipeline system. The system
has as inputs address bits, Read (R), and Write (W) signals. Based on the address and the
read/write signals, the system should be able to read, write (store) data in the memory.
Implement pipeline in your system, so that it is capable of doing the above operations
every clock cycle.
Turn in a system block diagram with well labeled blocks and detailed descriptions
of each block’s function and proposed timing approach.
Due: Nov. 21, 2008
Points: 15
Identify the basic cells necessary to build each block of your system. Provide circuit
schematics of these basic cells. Create layouts of these basic cells, and simulate them to
verify their functionality.
Turn in a write up with these schematics, layouts and simulation results.
Due: Dec. 5, 2008
Points: 45
Complete the system layout. Make sure the entire system fits in the pad frame. Available
area in pad frame is 3000λ × 3000λ.
Due: Dec. 10, 2008
Points: 25
Simulate you system using Spectre with suitable test vectors. The simulation results
should prove the system’s capability in reading, writing and storing data. Your system
should be able to perform these operations every clock cycle.
Due: Dec. 18, 2008
Turn in your final report
3. Final Report
Final report must have an introduction, system description, clock approach, circuit
design, circuit layouts, simulations at system level, testing approach (state how you
propose to test the physical chip), conclusion and references (bibliography).
EE466 VLSI Design
Term Project
Option 2
Due: Dec. 18, 2008
Objective
The standard-cells based design is one of the most prevalent full custom design styles. In
this design style, all of the commonly used logic cells are developed, characterized, and
stored in a standard cell library. A typical library may contain a few hundred cells
including inverters, NAND gates, NOR gates, memory cell, latches, and flip-flops. Each
gate type can have multiple implementations to provide adequate driving capability for
different fanouts. For instance, the inverter gate can have standard size transistors, double
size transistors, and quadruple size transistors so that the chip designer can choose the
proper size to achieve high circuit speed and layout density.
For ease of cell placement and inter-cell routing (wires) in a large layout, each cell layout
is designed with a fixed height, so that a number of cells can be placed side-by-side to
form a grid layout. The power and ground rails typically run parallel to the upper and
lower boundaries of the cell, so that all cells in a row can share a common power and
ground rails. The nMOS transistors are located closer to the ground rail while the pMOS
transistors are placed closer to the power rail. The objective of this project is to layout,
simulate and characterize various logic cells for a standard cell library.
Description
In this project you can choose one among the following options. Each of these options
has two cells. For the option you have chosen you are required to create layouts for both
the cells. The layouts must be optimized for area, power, and performance (switching
speed, drive strength). You must also provide a comparison between the two cells in
terms of functionality and performance.
Option 1: Decoupled Dynamic Content Addressable Memory Cells
Refer to the paper:
J. G. Delgado-Frias, J. Nyathi, S. B. Tatapudi, “Decoupled Dynamic Ternary Content
Addressable Memories,” IEEE Transactions on Circuits and Systems-II, Volume 52,
Issue 10, Oct. 2005, pp: 2139 - 2147
Implement the cells (a) 7.5-T DDCAM cell and (b) 10.5-T DDCAM cell.
Option 2: Dual-Edge Triggered Storage Elements
Refer to the paper:
“Dual-edge triggered storage elements and clocking strategy for low-power systems”
Nedovic, N.; Oklobdzija, V.G.; Very Large Scale Integration (VLSI) Systems, IEEE
Transactions on Volume 13, Issue 5, May 2005 Page(s):577 - 590
Implement the cells (a) Transmission-gate latch-MUX and (b) CMOS latch-MUX.
(pg. 583)
Option 3: Delay Elements
Refer to the following papers:
An empirical and analytical comparison of delay elements and a new delay element
Design Mahapatra, N.R.; Garimella, S.V.; Tareen, A.; VLSI, 2000. Proceedings, IEEE
Computer Society Workshop on 27-28 April 2000 Page(s): 81 – 86
Implement the (a) Thyristor based delay element
A digitally programmable delay element: design and analysis
Maymandi-Nejad, M.; Sachdev, M.; Very Large Scale Integration (VLSI) Systems, IEEE
Transactions on Volume 11, Issue 5, Oct. 2003 Page(s):871 – 878
Implement the (b) Digitally controlled delay element
Option 4: 1-bit Full Adders
Refer to your text book Chapter 10:
Implement the (a) CMOS full adder (pg. 640) and (b) Transmission gate full adder
(pg. 643)
Note
All the above papers can be found on IEEE Xplore. Please go to www.ieee.org, and use
the IEEE Xplore to search for the papers mentioned.
Milestones
Milestones are used to ensure the timely and successful completion of the project. Please
observe the following milestones. No extensions will be given on milestones.
Milestone 1: Study of the cells to be implemented, implementation and simulation plan
Due: Nov. 14, 2008
20 points
You have to provide a detailed implementation and simulation plan (inputs, outputs, input
drive used, output drive achieved etc.) for the cells you chose to implement. These will
help in the layout and simulation of the cells. In simulation plan you should provide
signals that would constitute the cell test patterns and the expected outputs. This could be
just logic values. Vector inputs for all the possible input patterns should also be provided.
Milestone 2: Complete layout and functional test of the cells.
Due: Dec. 10, 2008
30 points
You have to provide the completed layouts along with the functional test of the layouts.
In the functional test you have to prove that the cell is in working condition.
Milestone 3: Final report
Due: Dec. 18, 2008
50 points
A report with the detailed description of the cells implemented, working of the cells,
detailed simulation results for the power, performance of the cell. Area optimizations
must also be included in the final layouts and a discussion on the performance gains
achieved due to such optimizations.