Tat Kee Tan
260 N. Mathilda Ave #N7
Sunnyvale CA 94086
Tel: 1-408-9666018 Email: tantatkee@gmail.com
Education
1) 2000-2003: Princeton University, Electrical Engineering (CE), Ph.D., Advisor: Prof. Niraj Jha
2) 1998-2000: Princeton University, Electrical Engineering (CE), Master of Art, Advisor: Prof. Niraj Jha
3) 1991-1995: Nanyang Technological University, B.Eng. (1st Class), Advisors: Prof. K. Arichandran, Dr. Y. L. Lu.
Relevant Courses in Princeton
Theory of Algorithms, Computer Architecture, Low Power IC and System Design,
Solid State Physics, Electronic Devices, VLSI Design, Distributed Computing and Networking,
Operating System, Digital Signal Processing.
Industrial Experiences
1) 7/1995-6/1997 : Motorola Electronics Pte Ltd, Singapore, Software Engineer. Experiences include:
i) development of pager decoder firmware and ASIC,
ii) troubleshooting of finished prototype and providing support for the production pilot-run.
2) 6/1997-7/1998 : SGS-THOMSON Microelectronics, Singapore, IC Design Engineer. Experiences include:
i) customized analog IC design using BCD (BiCMOS-DMOS) process. Product : Power Combo - Analog control
system driving hard disk spindle and voice coil motor. Specific sub-circuits: bandgap reference, op-amps, controller
loop, D/A converter, custom logic circuits,
ii) discussion of specific requirement with customers and troubleshooting of prototype die.
3) 1/2004-Present : Magma Design Automation, Inc., Santa Clara, CA, Member of Technical Staff. Experiences
include:
i) developing algorithms for high-level and logic optimizations aiming to improve timing and area of synthesized
logic circuits, e.g., SDC and ODC optimizations, rewiring of redundant logic,
ii) developing new ideas for early logic optimizations, targeting low memory consumption (peak and used) and runtime,
iii) working with product engineers to promptly resolve customer specific requests.
Research Experiences (Ph.D. thesis: High-level energy analysis and optimization of OS-driven embedded
software)
1) Built an energy simulation framework (EMSIM) for an Intel StrongARM-based platform. This simulator models
a system in sufficient details so as to allow execution of the embedded Linux OS in the simulated environment.
URL: http://www.princeton.edu/~cad/emsim
2) Built a software synthesis framework for energy efficient OS-driven multi-process embedded software. The
synthesis tool takes as input a behavioral specification called the control-data flow diagram (CDFD) and generates a
multi-process C program that is energy-optimized in terms of its software architecture.
Research Experiences (Non-thesis)
1) Studied various low-power and low-energy design techniques for hardware and software.
2) Jointly implemented IMPACT, a behavioral synthesis tool for low power ASIC. IMPACT is currently being
commercialized by Alternative System Concepts (ASC).
URL: http://www.ascinc.com/products/low_power/lowpowertool.html
Teaching Experiences (at Princeton University)
1) Teaching assistant for ELE208, Integrated Circuits: Practice and Principles.
2) Teaching assistant for ELE402, Digital Electronics.
Conference Publications
1) T. K. Tan, A. Raghunathan, G. Lakshminarayana, and N. K. Jha, “High-level software energy macro-modeling,”
Proc. Design Automation Conference, June 2001, pp. 605--610.
2) T. K. Tan, A. Raghunathan, N. K. Jha, “EMSIM: An energy simulation framework for an embedded operating
system,” in Proc. Int. Symp. Circuit & Systems, May 2002, pp. 464--467.
3) T. K. Tan, A. Raghunathan, N. K. Jha, “Embedded operating system energy analysis and macro-modeling,” in
Proc. Int. Conf. Computer Design, Sept. 2002, pp. 515--522.
4) T. K. Tan, A. Raghunathan, N. K. Jha, “Software architectural transformations: A new approach to low energy
embedded software,” in Proc. Design Automation & Test in Europe, Mar. 2003, 1046--1051.
5) W. Wang, T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S. Vallerio, L. Zhong, A. Raghunathan, and N. K. Jha, “A
comprehensive high-level synthesis system for control-flow intensive behaviors,” in Proc. Great Lakes Symposium
on VLSI, April 2003.
6) T. K. Tan, A. Raghunathan, and N. K. Jha, “An energy-aware synthesis methodology for OS-driven multi-process
embedded software,” in Proc. Int. Conf. Embedded Systems & Applications, June 2004.
Journal Publications
1) T. K. Tan, A. Raghunathan, N. Jha, “High-level energy macro-modeling of embedded software,” IEEE Trans.
Computer-aided Design of Integrated Circuits and Systems, 21(9) 1037-1050, Sept. 2002.
2) T. K. Tan, A. Raghunathan, N. Jha, “A simulation framework for energy consumption analysis of OS-driven
embedded applications,” IEEE Trans. Computer-aided Design of Integrated Circuits and Systems, 22(9) 1284-1294,
Sept. 2003.
3) T. K. Tan, A. Raghunathan, N. K. Jha, “Embedded operating system energy analysis and macro-modeling,” to
appear in ACM Trans. Embedded Computing System.
Undergraduate Publications
1) Y. L. Lu, J. L. Ying, T. K. Tan, K. Arichandran, “Electromagnetic and thermal simulations of 3-D human head
model under RF radiation by using the FDTD and FD approaches,” IEEE Trans. Magnetics 32 (3) 1653-1656, May
1996.
Award
1) Motorola PPG (Paging Product Group) Award, 1997.
Skills
1) Programming environments: Unix, Linux, Windows
2) Programming languages: C/C++, Verilog, VHDL, Matlab, Labview
3) Configuration management tools: Clearcase, CVS.
4) IC design tools: comfortable with Cadence and Synopsys design environments.
5) Electronic instruments: oscilloscope, logic analyzer, etc.