Heat spreader for compliant FBG484
thermal interface
G. Visser 11/22/2014
The carrier board FPGA in Xilinx FBG484 package has a back-of-bare-die thermal interface. This can give
excellent performance with a small, floating air cooled heatsink, which is the normally recommended
approach. Conduction cooling is not even given a mention in the Xilinx documentation.
For the carrier board though we need conduction cooling, and this requires some mechanical
compliance, both to take up manufacturing tolerances and even more importantly to avoid stress due to
thermal expansion or other strains imposed on the assembly.
An appropriate compliant thermal interface might for example be a 1 mm gap into which Bergquist “Gap
Filler 4000” is introduced and cured. It is a low-stress, room temperature cured material with thermal
conductivity 4.0 W/m*K and hardness 75 Shore OO (similar to rubber band material). There is also a yet
softer, but slightly less conductive material “Gap Filler 3500S35”.
At the meeting last week when we discussed the thermal interface to the carrier FPGA it was said that
such material would not work, an order of magnitude higher thermal conductivity would be needed,
owing to the small thermal contact area 9.1 × 9.7 mm2 on the package. I believe on the contrary though
that it can work reasonably well if a small heat spreader is first bonded to the FPGA directly with a thin
but non-compliant interface. The goal here is to check and expand on that statement.
The problem (and the larger problem including the cooling bracket too) really needs a 3-d finite element
analysis, but I do not have the tools to do that. But the basic idea, and I believe even the necessary
dimensions of the heat spreader, can be determined from a 1-d analysis in cylindrical coordinates with
some simplifying assumptions.
The 9.1 mm × 9.7 mm die may be replaced with a 10.6 mm diameter circular die of about the same area.
I will fudge it a bit more to call it 12 mm diameter because I’m working on a 1 mm grid, I don’t think that
makes too much difference. The package heat spreader would probably be chosen about the size of the
package, and probably would be just as well to assume a circular shape since the corners won’t
contribute too much. Anyway here we will assume a circular shape, 32 mm diameter (which is about the
diagonal of the FBG484 package).
The power is assumed to be 7 W.
The heatsink side of the compliant interface is assumed to be isothermal. This could be modelled too, of
course. Hopefully it’s not a very bad assumption over the 16 mm radius of the spreader.
Here is a 1-d finite element calculation in LTSpice:
The voltages at nodes a1, a2, a3, …, a16 represent the temperatures of the die & heat spreader at radius
1, 2, 3, …, 16 mm. The nodes up to 6 mm received input power (current in the SPICE model) according to
their area. All nodes feed power (current in the model) to their neighbor according to the thermal
conductivity of the spreader (copper) and to the heatsink according to the thermal conductitivity of the
thick interface.
Here are the parameters. All in SI units. “m” means milli, e.g. mm, not meters!
.param pd={7/(pi*(0.006)**2)}
power density W/m2
.param sigma_goop=4
thermal coductivity of gap
.param t_goop=1m
thickness of gap
.param sigma_pl=381
thermal conductivity of spreader
.param t_plate=0.508m
thickness of spreader
Results
The Y axis is temperature (of the spreader – die temperature is ~1.5 degrees hotter where that is). The X
axis is radial position in mm.
Even an impractically thin 10 mil spreader makes a huge difference.
I think a 32 mil copper disk 32 mm in diameter (sorry for the mixed units there…) would be a good
choice. Yes, this subtracts 32 mils from the available thickness of the main heatsink part but I think there
it makes less impact than it does in the spreader role.
I will put some (again oversimplified of course) model of the heatsink in this just to see how that looks.
But I don’t think the conclusion will change much.
Real 3-d calculations are needed with the real geometry to really check and optimize this stuff. I can’t do
that.
By the way, no doubt this oversimplified 1-d model is exactly solvable but I didn’t bother to figure out
the details there, it was just simpler to do it with SPICE. But would be a better write-up if we just solved
the equations, for sure.
Appendix
1. For bonding the heat spreader to the FPGA die, something like TIMtronics TIM-813HTC looks
good. An epoxy of modest thermal conductivity that can make a good thin bond will work well.
This is 2.7 W/m*K. I think a 50 µm bond is practical but would have to be tested & confirmed.
For our power density of 79.3 kW/m2 the temperature rise is 1.47 degrees.
2. I think the best way to install the compliant gap fill material is to have a small hole like 1/8th inch
in the heatsink on center over the FPGA. Once installed to the board by soldering, the gap fill
material can be injected through that hole until it is visually confirmed to run out the sides
around the FPGA spreader. (Or a defined amount could be injected.)
3. Berquist states: “Primarily for aerospace applications, outgassing data is detailed in Bergquist
Application Note #117, tested per ASTM E595.” We should probably look at this, but I hope it is
not an issue since the electronics compartment is anyway isolated from the quartz, right?