San José State University
Department of Electrical Engineering
Proposed syllabus for Minor modified EE227
“Signal Integrity in AMS Integrated Circuits, Design and Modeling”
Proposed by:
Shahab Ardalan
Prerequisites:
EE221
Course Description:
This course studies essential blocks for wire-line communication integrated circuits such as analog
equalizer circuits, Decision-Feedback Equalization (DFE), Phase Looked Loop (PLL) and Clock and
Data Recovery (CDR) circuits. True understanding of system level modeling and behavioral of the
PLL will be discussed. Matlab/Simulink Modeling techniques will be introduced as new vehicle for
system level design and simulation. Performance metrics such as random jitter, BER, jitter transfer
jitter tolerance, phase noise and … will be introduced. Integrated circuit design consideration for the
key essential blocks for PLL and equalizer block will be covered.
Required Textbook:
“Design of Integrated Circuits for Optical Communications”, B. Razavi, McGraw-Hill, 2002
Other Reference Materials:
“Phase-Locking in High Performance Systems from Devices to Architectures”, B. Razavi, IEEE
Press, 2003 (Available on IEEE Explorer)
Course Goals:
1. Students will be able to model, analyze and design different architecture for Phase locked
Loop (such as type-1, type-2, hybrid PLL, Digital PLL, DLL, ILO-PLL, PI-PLL)
2. Student will be able to model, analyze and design analog and digital line equalization circuits.
Proposed syllabus for EE227, “Signal Integrity in AMS Integrated Circuits, Design and Modeling”
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3. Students will be exposed to challenges and limitation of existing circuits and topologies.
4. Students will be able to understand the concept of Jitter tolerance, Jitter transfer, Jitter
peaking, random jitter, phase noise, BER and …
5. Students will be able to use modern engineering modeling CAD tools for computations,
modeling, simulations, analysis, and design.
6. Students will be able to verify the theory with hands-on lab simulations.
Grading:
Midterm exam 30%
Design project 30%
Final exam 40%
Grading Percentage Breakdown:
90% and above A
89% - 85% A84% - 82% B+
81% - 79% B
78% - 75% B74% - 72% C+
71% - 69% C
68% - 65% C64% - 62% D+
61% - 59% D
58% - 55% D
below 55% F
Exams:
Exams will be closed book. However, students are allowed to bring 1 page of aid sheet. There will be
no make-up exam and those absent will receive no credit. Students must write their answers clearly in
an organized fashion. Further instructions will be provided during exams.
Projects:
Projects are mainly based on system level modeling in Simulink and circuit implementation on
Cadence and are closely relate to topics discussed in this course. Cadence will not be taught in this
course and students are required to master this CAD tool by themselves. However the cadence
Proposed syllabus for EE227, “Signal Integrity in AMS Integrated Circuits, Design and Modeling”
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tutorial is available on the course website. Each group (maximum 3 students) must write a formal
project report using a word processor (i.e. Microsoft Office) and submit the original write-up
including all data, images and graphs in a CD and by email before deadline to be eligible to receive a
credit. Students may be required to present their works similar to standard design reviews as
conducted in industry. More details on design projects will be provided as the lectures progress
Academic Integrity Statement:
Your own commitment to learning, as evidenced by your enrollment at San Jose State University, and
the University’s Academic Integrity Policy requires you to be honest in all your academic course
work. Faculty members are required to report all infraction to the Office of Student Conduct and
Ethical
development.
The
policy
on
academic
integrity
can
be
found
at
http://sa.sjsu.edu/student_conduct Students in this course are expected to maintain high ethical
standards in all matters pertaining to the course, including, but not limited to, examinations,
homework, course assignments, presentations, writing, laboratory work, team work, treatment of
class members, and behavior in class. Cheating and plagiarism are violations of the SJSU Policy on
Academic Dishonesty (S98-1) and will not be tolerated in the class. Students are expected to have
read the Policy, which is available at http://www2.sjsu.edu/senate/S014-12.pdf
Campus Policy in Compliance with the Americans with Disabilities Act:
If you need course adaptations or accommodations because of a disability, if you have emergency
medical information to share or if you need to make special arrangements in case the building must
be evacuated, please make an appointment with your course instructor or see him/her during office
hours as soon as possible.
Course Learning Objectives:
1. Understanding equalization concept in wire-line communication circuits.
2. Understanding phase locking techniques and clock and data recovery concepts.
3. Understanding performance metrics such as Jitter tolerance, Jitter transfer, Jitter peaking,
random jitter, phase noise, BER and …
4. The ability to model equalizer, PLL and CDR using Matlab/Simulink
5. The ability to design essential circuit block for data communication such as phase detectors,
charge pump, loop-filter, Ring and LC-tank voltage controlled oscillators, boosting filters,
DC restoration.
6. Understanding mechanism and procedures for testing a phase locked loop
Proposed syllabus for EE227, “Signal Integrity in AMS Integrated Circuits, Design and Modeling”
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Tentative Course Schedule:
Lecture
Topic
Lecture - 1
Introduction to wire-line communication
Lecture – 2
Introduction to equalization and phase locking concept
Lecture – 3
Phase Detectors
Lecture – 4
Current Mode Logic
Lecture – 5
Phase Locked Loop- System level
Lecture – 6
Phase Locked Loop- Analog type-1
Lecture – 7
Phase Locked Loop- Analog type-2
Lecture – 8
Non-Linear Phase Locking-1
Lecture – 9
Non-Linear Phase Locking-2 (CDR)
Lecture – 10
Phase Detector Modeling in Simulink
Lecture – 11
Clock, Data Source and VCO modeling in Simulink
Lecture – 12
Linear PLL Modeling in Simulink
Lecture – 13
Non-Linear PLL Modeling in Simulink
Lecture – 14
Performance Metrics-1
Lecture – 15
Performance Metrics-2
Lecture – 16
Midterm
Lecture – 17
Introduction to Oscillation
Lecture – 18
LC Based VCO
Lecture – 19
Ring VCO
Lecture – 20
Phase Noise in VCOs
Lecture – 21
Phase Noise Modeling in Simulink
Lecture – 22
Advanced CDR Architectures-1 (Clock FWD, Embedded Clock, Delay Locked Loop)
Lecture – 23
Advanced CDR Architectures-2 (Phase Interpolation)
Lecture – 24
Advanced CDR Architectures-3 (Lock Injection)
Lecture – 25
Dual Loop Architectures
Lecture – 26
Analog Equalization
Lecture – 27
Decision-Feedback Equalization (DFE)
Lecture – 28
Design for Testability and Calibration in PLL
Lecture – 29
Project Demo and Presentation-1
Lecture – 30
Project Demo and Presentation-2
Lecture – 31
Final Exam
Proposed syllabus for EE227, “Signal Integrity in AMS Integrated Circuits, Design and Modeling”
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