ECE 507 Seminar (Winter 2014)
2.00–3.30pm Friday, February 7th, Room EB103
Parameter extraction for simulations:
silicon strength after thinning process
Helene Fremont, University of Bordeaux, France
Abstract
A methodological approach for predictive reliability, coupling measurements and
simulation was presented last year. Starting from a given microelectronic system or
test vehicle the geometrical parameters as well as the physical parameters have to
be determined either from the bibliographic data, but in many cases also by
measurements. This is particularly important for new materials, but also for wellknown materials like copper or silicon, whose properties may depend on their
processing. The mission profile has to be described as accurately as possible,
and/or the aging test conditions have to be set up. Experimental tests and finite
element simulations have to be run in parallel on a first well known configuration.
In both cases the failure criterion for breakdown has to be defined. This may be a
difficult step, as measurable parameters are not necessarily possible to compute:
for instance an open circuit occurring in a BGA has to be correlated with a quantity
of accumulated strain or energy. Similarly, a delamination cannot be electrically
measured, but can be associated with an interfacial stress level which can be
calculated. The presentation will focus on parameter measurements.
Silicon is a “well-known” brittle material; but its fracture strength depends
on several physical parameters such as thickness, surface toughness and quality of
edges. With the onset of ultra-compact packages, Systems in Package may include
stacked dies and mechanical sensors. Thus the thinning of silicon becomes
necessary, for example to reduce the total thickness or to increase the flexibility for
applications using flexible substrates. The risk of failure, especially die crack, is
often a major concern in the reliability of electronic packages. Therefore chip
strength assessment becomes necessary for the reliability prediction of packaged
components. In this paper, two types of mechanical tests namely three point bend
test and ball on ring test are used and compared to evaluate the risks of fracture of
a silicon die as a function of its thickness, and of surface quality induced by the
thinning process. Five thinning processes, and thicknesses from 300μm down to
80μm, are statistically evaluated.
Simulations Regarding the Reliability of
the Chip Package Interaction.
Kirsten Weide-Zaage, Gottfried Wilhelm Leibniz
Universität, Hannover, Germany
Abstract
The increasing demand, regarding to advanced 3D-packages and high performance
applications, accelerates the development of 3D-silicon integrated circuit, with the
aim to miniaturize and reduce cost. CoC (Chip-on-Chip) as one possibility for 3D
integration can be used for the vertical assemble of ICs. CoC structures base on a
direct connection of ICs on chip level with through silicon vias (TSVs) and micro
bump arrays (µBGAs) with new reliability aspects. The placement of the TSV in
the circuit design is one of the aspects to be looked on. The shrinking dimensions
of solder joints and the rising operation temperatures cause new risks to the
reliability of solder joints. The reliability of systems and components are affected
by thermal and thermal-electrical stress loads due to high temperature and high
current. This stress leads to degradation effects like electro-, thermomigration,
delamination and cracking due to thermal material property mismatch. Two new
phenomena are void formation and accelerated inter metallic compound (IMC)
growth due to electromigration (EM). During the development of a reliable micro
electronic system, migration induced reliability issues have to be considered on
chip and package level. Generally measurements are time consuming and
expensive. The simulation enables a more detailed interpretation of the stress test
results. Simulation results of PoP and Flip-Chip also µ-BGA and TSV structures at
different operation condition will be presented and show the good usability of
simulation in this frame.
All welcome
Biographies
Hélène Frémont is associate professor at the University of Bordeaux 1 in France.
Her research expertise is microelectronics reliability and failure analysis. She is
currently leading the PACE (Packaging, Assembly and Electromagnetic
Compatibility) team of the IMS laboratory (Integration from the Material to the
System) of the University of Bordeaux. She is member of the technical committee
of different CPMT-IEEE conferences and of the organizing committee of the
European Symposium on Reliability of Electron Devices, Failure Physics and
Analysis ESREF. She co-authored more than 120 scientific articles, including
journal and conference publications, book chapters and invited papers.
Kirsten Weide-Zaage is senior lecturer (Privatdozent) and senior scientist in the
field of microelectronics at the Faculty of Electrotechnic and Computer Science of
the Gottfried Wilhelm Leibniz Universität in Hannover, Germany. She studied
Physics with main topic Biophysics and made her PhD in Electrical Engineering.
She is working since 1991 at the Information Technology Laboratory as researcher
and leader of the simulation group ‘robust electronics’ in the field interconnect and
package reliability. She is member of the technical committee of the European
Symposium on Reliability of Electron Devices, Failure Physics and Analysis
ESREF. She is author of more than 80 scientific articles, including journal and
conference publications, book chapters a book and invited papers.