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PMU Physical Implementation with Cadence AoT
Mixed-signal Solution
ABSTRACT
Success in today’s electronics market place requires highly integrated
and low-cost solutions for various applications. Analog and
mixed-signal IP content is significantly increasing in SoC design that
in the past contained mostly digital circuitry. This situation creates
new challenges for design, integration, and verification. An increasing
amount of analog IP is really mixed-signal. With rapidly increasing
SoC capacity, such mixed-signal chip implementation with traditional
flow is a slow and laborious process that can lead to design errors
and numerous iterations.
Cadence is addressing this challenge by introducing a new flow which
draws on the strengths of the schematic-driven mixed-signal (AoT)
and netlist-driven mixed-signal (DoT) flows, in addition to fully
taking advantage of the cross-operation OpenAccess database to
allow users to easily access the design from both analog and digital
platforms and take advantage of the unique features of each
environment.
This paper presents how to use Cadence AoT mixed signal solution
<以上所有信息均为中兴通讯股份有限公司所有，不得外传>
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内部公开 Internal Use Only▲
on a PMU project. This solution helps engineers arrive at a higher
quality block placement, pin locations, routing interface nets, and
thereby lowering routing congestion. It reduces the number of
iterations between analog and digital designs, particularly during
prototyping, chip integration, full chip STA and early-and-late
small/big OA-based ECOs by Cadence AoT Mixed-signal Solution.
KEY WORDS
Mixed-signal, SoC, OpenAccess, Interoperability, Prototyping, VSR,
Full chip STA.
<以上所有信息均为中兴通讯股份有限公司所有，不得外传>
All Rights reserved, No Spreading abroad without Permission of ZTE
第2页