Mixed-Signal Challenges & Solutions
for advanced process nodes
Cadence Design Systems
Bruno Dutrey – September 22, 2009
Agenda
• Introduction on advanced process nodes
• Importance of design methodologies in deep submicron
technologies
• Mixed-Signal Challenges & Solutions
• CERN – Cadence partnership highlights
Why advanced node design?
Design starts % of total
Advanced node design starts increasing
0.35
0.18u
0.3
0.25
0.13u
• 3X growth in 65nm
0.2
65n
0.15
0.25u
0.1
90n
0.05
0
• 7X growth in 45/40nm
45/40n
32/28n
2005 2006 2007 2008 2009 2010 2011 2012
Source: IBS 03/09
Primary drivers
Higher performance, lower power, increased functionality
3
© 2009 Cadence Design Systems, Inc. All rights reserved.
Advance node design challenge
Quality of silicon %
Yield
enhancements
• Litho
• Etch
• Thermal
• Random
• Stress
Scheduled tape-out
Scale and
complexity
• Multi-core
• Production-proven PDKs
• IP
• Rules
• Models
• TechFiles
© 2009 Cadence Design Systems, Inc. All rights reserved.
Time
• Design size
Custom and
IP design
4
• CMP
• Analog and RF
• Multiple protocols
• Low-power
• ECO
• Manufacturability
Evolution of Mixed Signal Design
Technology Implications
Digital and analog
distributed
throughout design
Physical hierarchy
separates digital
and analog
Latest
Older Design
5
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Mixed-signal design
Risks and costs are exploding
 >50% of re-spins at 65nm due to mixed-signal functionality
– Re-spins costs can be $5M to $10M
– 4-5 spins typical for AMS with 6-8 weeks for each spin
 Level of mixed-signal design effort and expertise increasing significantly
– Mixed-signal elements require 50% of SoC design effort for 10% of transistors
– Increased engineering costs due to multi-domain teams
 Poor verification planning and methodology
– Mixed-signal verification not well integrated into SOC verification plan
– Lack of good mixed-signal modeling methodology leads to missed or late errors
 New requirements on SoC integration team
– Managing and verifying interactions between analog and digital
– “Black box” methodology is reaching its limit
Mixed-signal verification challenges
 Verification task is growing exponentially
–
–
–
–
Analog simulation performance limits MS SoC verification
Need to validate analog blocks in a digital context
Validate behavioral blocks to transistor level specifications
Support for different levels of abstraction for full chip verification is
mandatory
 Pin connectivity errors cause majority of re-spins
– Need to avoid errors like pin connection errors, inverted polarity,
incorrect bus order, connected to wrong power domain, etc.
 Lack of structured handoff between analog design and digital
verification environments
 Advanced low-power techniques are introducing new verification
challenges
Mixed-signal implementation challenges
 Concurrent design of floorplan, AMS IP and digital blocks
– No fixed reference for optimization, all blocks flexible
– Requires additional attention in floorplanning, simple black-boxes are limiting
 Efficient round-trip data transfers between teams
– Traditional use of LEF/DEF/GDSII is inefficient
– Single design database is required for ease-of-use
 Controlled automation
– Constraint-driven implementation enables rapid turnaround
 Low-power support for complex mixed-signal SoC designs
– Driven by CPF (design intent)
– Implementation and verification automatically controlled by CPF
 Noise analysis concerns with sensitive analog circuits
– Digital simultaneous switching noise plus analog generated noise
– Transmitted through interconnect, substrate and package/board
Cadence overview
Build complete solutions for pressing challenges
Solution Offerings
System Development
Ecosystem
Enterprise Verification
Low Power
Mixed Signal
Advanced Node
Service Offerings
Systems
Design outsourcing
Foundry
Infrastructure
outsourcing
IP
Design environment
Enablement
EDA Partners
Methodology
enhancement
Standards
Hosted and managed
design solutions
Alliances
Design fundamentals
(Training)
Cadence overview
Build complete solutions for pressing challenges
Solution Offerings
Mixed Signal
Ecosystem
Service Offerings
Systems
Design outsourcing
Foundry
Infrastructure
outsourcing
IP
Design environment
Enablement
EDA Partners
Methodology
enhancement
Standards
Hosted and managed
design solutions
Alliances
Design fundamentals
(Training)
Cadence mixed-signal design verification
Comprehensive solution spans different use models
Mixed-signal SoC
Mixed-signal IP, IC
Virtuoso® platform
Integrated GUI
Incisive® platform
Integrated simulation engines
Verification
engineer
Analog
designer
Common verification methodology
• Continuous simulation performance
improvements e.g. Spectre®,
Spectre Turbo, APS, UltraSim, AMS
Designer, etc
• Real-value modeling (RVM)
• Cross-domain connectivity
• Low-power support
• Boost top-level mixed-signal
verification using RVM
• Model analog blocks in digital
context for full-chip verification
• Digital-centric MS regressions runs
• Metric-driven methodologies applied
to mixed-signal SoC verification
Virtuoso digital implementation option
Perfect for “analog-on-top” design flows
Constraints
Library
Synthesis using
RTL Compiler
Implementation in VDI
Placement
Optimization preCTS
Clock tree synthesis
Optimization postCTS
Routing
V
D
I
Add filler cells
Draw top level floorplan
in Virtuoso LS GXL
Design
O
P
E
N
A
C
C
E
S
S
2.2
Verification
VDI uses Encounter and Nanoroute technology
12
2009
Copyright Cadence Design Systems, Inc
Chip finishing in Virtuoso
V
I
R
T
U
O
S
O
Mixed-Signal flow without
with OA OA
Tcl Scripts
Verilog Netlist
Schematic
CDK
Timing Constr
RTL Compiler
(synthesis)
Timing Constr
(SDC)
RTL
Timing Library
(.lib)
capTable
Virtuoso
Chip Floor Planning
LEF
Configure
Physical
Hierarchy
Silicon
Virtual
Prototyping
I/O Placement
Block
Placement
Timing
Optimization
Encounter
Digital Block
Implementation
Pin
Optimization
Clock Tree
Synthesis
NanoRoute
or WRoute
LEF
(Antenna DEF Verilog GDS2
+ Power)
FE Analysis
FE Metal Fill
FE Verify
SPEF SDF
Hierarchical
Floorplan
OpenAccess
Virtuoso
Analog Block
Implementation
UltraSim
Virtuoso XL
Abstract
Assura
DRC/LVS
Assura RCX
Virtuoso
Top-Level Implementation and Analysis
VCAR
Assura
Assura
(Power +
Signal
Routing)
DRC/
LVS
RCX
AMS
Simulation
Improved MSoT Analysis
Future Development
• Traditional design flow
– Digital tools do not “see”
inside AMS block
– Lumped RC and .lib not
accurate
– STA cannot accurately verify
entire path
• With improved design flow
D/A Boundary Verification
7.1
Impossible to verify entire path
Abstracted for
Timing/SI
AMS Black-box
Digital
Move access point to first instance
8.1
– AMS partition “flattened”
– Route and verify net to first
instance in analog partition
– Verify Timing/SI accurately
Verify,
set constraint
AMS Partition
Digital
Foundry support for IC 6.1
The momentum continues to grow for SKILL PDKs
Cumulative
Growth in Foundry PDKs for IC 6.1
37 PDKs from
10 foundries
spanning
28nm to 0.35um
40
Number of IC 6.1 PDKs
35
X-FAB
UMC
TSMC
Tower
SMIC
LFoundry
Jazz
IBM
Chartered
AustriaMicroSystems
30
25
20
15
10
5
0
3Q08
15
2009
4Q08
Copyright Cadence Design Systems, Inc
1Q09
Time
2Q09
PDK migration – CDBA to Open Access
The Five Biggest Challenges
•
•
•
•
•
Technology File
Vias
SKILL
Pcells
Tool Interoperability
CERN – Cadence partnership
Needs and challenges
• Formalize & Automate Cern Mixed-Signal design flow based on IBM
open access PDK
– Build Open Access PDK supporting advanced features
– Productivity enhancement
• Focused on Client’s Design Team Productivity through VCAD IPs
– IP packaging
– Design environment
• Interoperability based on IBM pdk
– Currently implementing a CERN design on the developed
• Training Services
Mixed-signal services
Solutions focus overview
Production-Proven Methodology
Offerings
• Custom PDK development environments
• Full Chip Functional Verification
• Top Down Mixed Signal Implementation
• Design Signoff and Validation Flow
• Complete Design Environment
Management
Mixed-signal Design
Packaged Services Offerings
• Data Sheet PDK
• Mixed-signal Functional Verification
• Custom Library Characterization
• Design IP
Technology Transition Offerings
45
40
• High Speed IO and SerDes
• Analog Front-end
• Custom RFIC
• High Perf Blocks (ADC, DAC, PLL, …)
• Complex Block Porting
>100 tape-outs in
• Competitivelast
replacement
4 years
• 6.1 feature adoption
97% first pass
• Moving to Advanced Nodes
• Design Firstsuccess rate
35
30
25
20
15
10
5
0
SiGe
18
2009
Copyright Cadence Design Systems, Inc
180nm
130nm
90nm
65nm
40nm
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