Concurrent, OA-based Mixed-signal
Implementation
Mladen Nizic
Eng. Director, Mixed-signal Solution
© 2011, Cadence Design Systems, Inc. All rights reserved worldwide.
Mixed-Signal Design Challenges
Traditional model
“Over the Wall”
Collaborative
model
Floorplan
Architect
Results of World-wide MS ToT survey of 561 attendees; Q1-2011
Abstract
Floorplan
Concurrent
block design
Integration
lead
Analog/Custom
group





Digital
group
Data translation
Setup & maintenance for multiple tools
Informal communication of design intent
“Black-box”: no visibility in each other domain
Sequential design tasks
Increased iterations  Prolong TAT
Costly ECO  Sub-optimal design
Increased risk of silicon re-spin
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© 2012 Cadence Design Systems, Inc. All rights reserved.
Integration,
ECO, Signoff
•
•
•
•
•
Common DataBase for analog and digital
Unified technology setup
Constraints drive design
Full transparency of each domain
Relative importance
Concurrent design
Fewer iterations Shorten TAT
Effective ECO  Quality design
Reduced risk of silicon re-spin
Biggest Challenges in MS Implementation
Weighted Importance
World-wide survey of 561 MS ToT attendees, Q1-2011
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© 2012 Cadence Design Systems, Inc. All rights reserved.
Schematic-driven Mixed-signal Flow Evolution
Traditional
OA-integrated
Analog-centric
 Unified database – no data translation
 Full visibility into analog and digital,
 Digital in separate hierarchy
 Separate analog and digital environments
 Black-box/Abstract/GDS level exchange
 Data translation
Virtuoso
3rd Party
P&R tool
OA
Proprietary DB
Virtuoso
EDI
Concurrent
 Highest level of mixed-signal integration
 Digital instantiated in layout module hierarchy
 and bind to schematic at the top level
Virtuoso
OA
Digital
OA
Digital
Digital
Digital
MS architecture
and integration
1st generation
30% Productivity Gain
EDI
Digital
Digital
2nd generation
30% Productivity Gain
Unified Environment for MS Design
Area
Productivity
No
Data floorplanning
translation
Better
Virtuoso
TATEDI
Productivity
Effective
ECO
No Data translation
at
any design stage
Quality of Silicon
Productivity
Avoid
re-spins by
No Data translation
better timing signoff
Productivity
Productivity
Design
constraints
No Data translation
passing
OpenAccess
Productivity
No Data translation
Unified Design DataBase
Efficiency
Maintain one instead of
two technology setups
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Unified Library and Technology setup
© 2012 Cadence Design Systems, Inc. All rights reserved.
Mixed-Signal PDK
Virtuoso
Optional for
digital users
EDI
techLEF
OA techfile
One time
consolidation
• One time effort on consolidating technology information for OA interoperable MS
Implementation flows
• Taking advantage of Incremental Technology Data Base (ITDB)
• Single, consolidate OA techfile for both Virtuoso and EDI
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© 2012 Cadence Design Systems, Inc. All rights reserved.
Mixed-signal Implementation Flows
A
A/d
A/D
D/A
D/a
D
Methodology
Analog-centric
Concurrent
Digital-centric
Design
Top level is analog; standard cell
contained in block
Analog and standard cell digital mixed
at same level.
Predominantly digital design with
analog integrated as macros
Top level
connectivity
Schematic
Schematic and Netlist
Netlist
Verification
SPICE; Mixed-signal simulation,
analog behavioral models
Mixed-signal simulation; behavioral
models; Assertions and MDV
Digital simulation with RNM; MDV
Floor-planning
Controlled, constraint driven
Control and automation
Highly automated, timing,
congestion, power driven
Analog content
Main/Top
Co-designed
Separate partition
Digital content
in separate partition
Co-designed
Main/Top
Routing
Custom for top and analog.; timingdriven on-grid for digital
Combination of custom of-grid and
digital on-grid
Top level analog by VSR; all other
routing by NR.
Chip Integration
Custom Environment
Custom or Digital
Digital environment
Full-chip Signoff
Mixed-signal parasitic simulation
STA and/or Mixed-signal parasitic
simulation
STA
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© 2012 Cadence Design Systems, Inc. All rights reserved.
AMS IP Implementation Flow
Top Level Floorplan
RTL netlist
Library
Constraints
DFT Test Insertion
Floor planning
Analog/Custom
Blocks
Power Planning
Top Level
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© 2012 Cadence Design Systems, Inc. All rights reserved.
Placement
Clock Tree Synthesis
Timing optimization
Routing
Physical Verification
DFM
OpenAccess
Chip Integration
& Signoff
Low Power Optimization
Synthesis
Mixed-signal Floorplanning
Top Level Floorplan in Virtuoso
 Encounter and Virtuoso
interoperate on refining
floorplan using
constraints:
−
−
−
−
−
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Pin fixed or locked
Halo
Density screen
Group and region
Placement status of an
instance
© 2012 Cadence Design Systems, Inc. All rights reserved.
Digital
Timing driven
Placement
and pin Optimization
Block floorplan in Encounter
Mixed-Signal Constraint Interoperability
 Specification and capture of MS
design integration intent
 Hierarchical manipulation of
integration constraints
 Storage and delivery through OA db
 Implementation support within both
EDI System and Virtuoso
 Signoff validation using PVS
 Phase 1 support for MS routing
constraints
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© 2012 Cadence Design Systems, Inc. All rights reserved.
Timing & SI Signoff Analysis for Mixed-Signal
• Challenge:
• Full chip STA signoff should cover paths through
digital embedded in AMS blocks
• No visibility into AMS “black-box” during integration
• Timing model for AMS blocks are inaccurate, do
not account for SI and hard to generate
 Solution:
•
•
•
•
•
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Bring AMS blocks to EDI system via OA
Expose its digital content (instances, layout routing) and stitch it to top level
Extract and time full chip design including digital from AMS blocks
Perform SI analysis
No need for timing (.lib) models for AMS blocks (besides std. cells)
© 2012 Cadence Design Systems, Inc. All rights reserved.
ECO for Mixed-Signal SoC Design
Pre-Mask ECO Flow
Analog
PCell
 Pre and post mask ECO functionality
available in EDI
Load (OA) design
(restoreOaDesign)
Output and edit
Verilog netlist
Full OA DB
Set OA update mode
setOaxMode -UpdateMode true
− Save time by avoiding block level changes
ecoOaDesign
and repeating integration
Connects the global net
applyGlobalNets
Connections for new instances
 Highly automated
− No manual work
− EDI does re-mapping
If new Tie Hi/Tie Lo
Connections are required
addTieHiLo
ecoPlace addFiller
ecoRoute
Save design
(saveOaDesign)
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© 2012 Cadence Design Systems, Inc. All rights reserved.
ECO steps
− Post-mask use spare cells, and limits eco
routing to only specific layers
 Performed on design’s unified OA
database
Stdceell OA
Libraries
Benefits of Cadence MS Implementation Solution
Predictability
Productivity
Productivity
Productivity
TAT
TAT
TAT
Predictability
Productivity
Predictability
Mature, Proven Analog and Digital design platforms
Common OA Database and unified technology setup
Constraint driven methodology
Easy to adopt and use
Powerful Floorplanning/Pin-optimization
Integrated analysis/signoff
Automated ECO flow
Strong Ecosystem
Ability to serve entire scope (A<>A/d<>A/D<>D/a<>D)
Support and Services
Modern Mixed-signal design raises new challenges,
Cadence is your best partner in addressing them.
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© 2012 Cadence Design Systems, Inc. All rights reserved.
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© 2012 Cadence Design Systems, Inc. All rights reserved.
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© 2012 Cadence Design Systems, Inc. All rights reserved.