Department of Electrical & Electronic Engineering
ORT Braude College
Advanced Laboratory for Characterization of Semiconductor Devices - 31820
Capacitor
MOS
February 9, 2016
Dr. Radu Florescu
Dr. Vladislav Shteeman
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
The goal.
In this experiment, you will measure the Capacitance-Voltage (C-V) characteristics of a standard
MOS capacitor, integrated in a silicon wafer, and extract its main physical parameters using the
Agilent 4284A C-V analyzer.
The following parameters will be obtained from the C-V characteristics:
1.
Oxide layer capacitance Coxide
2.
Oxide layer thickness toxide
3.
Si substrate depletion layer capacitance in the inversion region CSi
4.
Threshold voltage Vth
5.
Minimal capacitance of the Si substrate in the depletion region, CSi,min
6.
Acceptors concentration in the substrate, N A
7.
Debye length LD
8.
Built-in bulk potential of the Si substrate  F
9.
Depletion layer width at the threshold voltage xd ,threshold
10. Flatband capacitance CFB
11. Flatband voltage VFB
12. Oxide traps charge Qtraps
Dr. Radu Florescu
Dr. Vladislav Shteeman
2
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Short theoretical background.
The MOS capacitor is a structure, consisting of
 Metal referred to as the gate (usually it is a heavily doped n+ - poly-silicon layer (poly-Si)
which behaves like a metal)
 Oxide (silicon dioxide, also called silica, SiO2)
 Semiconductor (n- or p- doped Si substrate)
Figure 1 shows sketch of capacitor MOS device. We will refer a MOS structure with p-type
substrate as an n-type MOS or nMOS capacitor (since the inversion layer - as discussed below – is
of n-type, i.e. contains electrons). Alternatively, the MOS structure with an n-type substrate is
called pMOS.
MOS capacitors are of fundamental importance in integrated devices such as MOS Field Effect
Transistor (MOSFET) and Charge Couple Device (CCD).
(gate contact)
(body contact)
Figure 1. Sketch of nMOS capacitor structure on p-type substrate (after [1]).
The capacitance value of capacitor MOS depends on the voltage that is applied to the gate
electrode V g . Note that applying a negative potential to an electrode ( Vg  0 ) is equivalent to
putting a negative charge on that electrode (see Figure 2(a)). Applying a negative potential moves
upward the Fermi level of the gate metal. Alternatively, applying a positive potential to an
electrode ( Vg  0 ) is equivalent to putting a positive charge on that electrode (see Figure 2(b,c)).
Applying a positive potential moves downward the Fermi level of the gate metal.
There are 3 main regimes of operation of capacitor MOS, separated by two voltages.
Dr. Radu Florescu
Dr. Vladislav Shteeman
3
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
The regimes are described by what is happening to the semiconductor-isolator interface.
These are (Figure 2):
(1) Accumulation, in which mobile carriers of the same type as the body [holes for nMOS and
electrons for pMOS] accumulate at the surface;
(2) Depletion, in which the surface is devoid of any mobile carriers, leaving only a space charge or
depletion layer; and
(3) Inversion, in which mobile carriers of the opposite (to the body) type [electrons for nMOS and
holes for pMOS] aggregate at the surface to “invert” the conductivity type of the semiconductor at
the interface.
The two voltages that demarcate the three regimes are (Figure 2):
(a) Flatband Voltage ( VFB ), which separates the accumulation from the depletion, and
(b) Threshold Voltage ( Vth ), which demarcates the depletion from the inversion
Vg  VFB
(a)
VFB  Vg  Vth
(b)
Vg  Vth
(c)
Figure 2. Charge regimes of an n-type Metal-Oxide-Semiconductor structure with p-type
substrate : (a) accumulation, (b) depletion and (c) inversion in equilibrium conditions (after [1]).
Detailed analysis of MOS capacitor regimes.
Flat band. The term “flatband” refers to fact that the energy band diagram of the semiconductor
is flat, which implies that no charge exists in the semiconductor. The flatband diagram of a typical
nMOS structure is shown on Figure 3. In this case Fermi level EF  const throughout the whole
Dr. Radu Florescu
Dr. Vladislav Shteeman
4
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
MOS structure. Note that the flat band voltage VFB must be applied to the MOS structure to
obtain this flat band diagram. The VFB is obtained when the applied gate voltage equals the
workfunction difference between the gate metal  M and the semiconductor  Semiconductor :
VFB   M   Semiconductor
(If there is also a fixed charge in the oxide and/or at the oxide-silicon interface, the expression for
the flatband voltage must be modified accordingly.)
Typical value of flat band voltage: for N A  1017 cm 3  VFB  0.97V .
Figure 3. Flatband energy diagram of an nMOS structure (after [1]).
At the flat band condition, the surface potential  S , being a difference between the Fermi levels
in semiconductor deeply inside the bulk and at the interface Si – SiO2 ,  S  Ei( bulk )  Ei( interface)  q ,
equals to zero:
S  0
(Since the bands are flat, Ei( bulk )  Ei( interface) .)
Consider in details 3 different bias regimes of capacitor nMOS.
1. Accumulation (Vg  VFB ). A negative gate voltage (which is equivalent to putting a negative
charge on that electrode (see Figure 2(a)) ) drains the majority carriers (in case of nMOS - holes
in p-type substrate) at the oxide-semiconductor interface.
Dr. Radu Florescu
Dr. Vladislav Shteeman
5
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Fermi levels EF are different in the metal and semiconductor (Figure 4). (Even though, those
Fermi levels EF are constant within the metal and within the semiconductor.)
Surface potential  S  Ei( bulk )  Ei( interface)  q under accumulation condition is negative, since
Ei( bulk )  Ei( interface)  0 (see Figure 4):
S  0
Thus, the bands bend upward (Figure 4).
Majority carrier concentration (in case of nMOS- holes) is given by:
p  x   ni e  Ei  EF  kT
px  increases near the surface. Therefore the regime is called accumulation.
Vg  VFB
Figure 4. Energy band diagram of nMOS structure biased in accumulation (after [1]). See
List of symbols in Appendix 1 for definitions of EC, Ei, EF, EV, ΦS and ΦF.
From Figure 4, it is clear, that a non-zero flat band voltage VFB is necessary to overcome the
band bending situation at equilibrium due to the difference of working function between
metal  M and semiconductor bulk  Semiconductor .
The total capacitance of the MOS structure Ctotal is defined only by the capacitance of the
oxide Coxide :
Coxide
Dr. Radu Florescu
Dr. Vladislav Shteeman
6
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Ctotal  Coxide  A
 0 oxide
toxide
[F ]
(where A is the capacitor area, toxide - oxide layer’ thickness,  oxide - oxide layer’ (relative)
dielectric constant and  0 - permittivity of vacuum; see also List of definitions in Appendix 1)
2. Depletion ( VFB  Vg  Vth ). Because of the positive gate voltage, Fermi level EF goes down in
the metal (gate). This positive gate voltage pushes out the majority carriers (in our case - holes)
from the oxide-semiconductor interface leaving a fixed charged layer (depletion layer) of
negative immobile ions (atomic nuclei of acceptors). This charge, which is located in the
semiconductor, compensates the positive charge on the gate.
VFB  Vg  Vth
Figure 5. Energy band diagram of nMOS structure biased in depletion (after [1]). See
List of symbols in Appendix 1 for definitions of EC, Ei, EF, EV, ΦS and ΦF.
Surface potential  S  Ei( bulk )  Ei( interface)  q under the depletion condition is positive, since
Ei( interface)  Ei( bulk )  0 (Figure 5):
S  0
Thus, the bands bend downward (Figure 5).
The depletion layer width, xd , growths with the gate voltage V g and  S .
xd 
Dr. Radu Florescu
Dr. Vladislav Shteeman
2 si 0
S
qN A
7
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
(where  Si  11.8 is the relative dielectric constant of Si, N A is acceptors concentration of in
the Si bulk, q - electron charge,  S - surface built-in potential in the semiconductor at the Si –
SiO2 interface; see also List of definitions in Appendix 1)
The extension of xd decreases the total capacitance of the device (see below).
The total capacitance of the MOS structure Ctotal represents a serial capacitance of the two
capacitors: oxide layer Coxide and depletion region in the semiconductor CSi :
1
Ctotal

1
Coxide
Coxide  A

Coxide
1
CSi
 0 oxide
toxide
CSi 
C Si
q 0 Si N A
2 S
(where  Si  11.8 is the relative dielectric constant of Si, N A is a concentration of acceptors in
the Si bulk, q - electron charge,  S - surface built-in potential in the semiconductor at the Si –
SiO2 interface; see also List of definitions in Appendix 1)
3. Inversion (Vg  Vth ). After some threshold voltage, increasing of V g does not result in the
extension of the depletion layer. The width of the depletion layer becomes maximal, xd ,threshold ,
and stays fixed. This gate voltage is referred to as threshold voltage,Vth . For Vg  Vth , the
concentration of the minority carriers (in case of nMOS - electrons), thermally generated in the
depletion layer, will be higher than the concentration of the intrinsic carriers. At some point
(onset of so-called strong inversion) this concentration will be equal to the concentration of the
majority carriers (in case of nMOS - holes). In other words, under inversion condition,
semiconductor at the Si-SiO2 interface becomes “artificially” strongly n-type, while in the bulk it
stays strongly p-type. The inversion layer at the Si – SiO2 interface screens the depletion layer
from further increasing in follow up the increase of V g . Therefore, the width of the depletion
layer reaches its maximum value xd ,threshold and does not grow more.
Surface potential  S  Ei( bulk )  Ei( interface)  q under inversion condition is positive, since
Ei( interface)  Ei( bulk )  0 (Figure 6):
S  0
Dr. Radu Florescu
Dr. Vladislav Shteeman
8
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Thus, the bands bend downward (Figure 6).
The onset of strong inversion corresponds to the following condition:
 S  2 F
where  F  Ei(bulk )  EF  q is a built-in potential of the Si deep inside bulk.
The depletion layer width xd ,threshold is maximal and does not change:
xd ,threshold 
2 0 Si  S
qN A

 S 2  F
4 0 Si  F
qN A
Vg  Vth
Figure 6. Energy band diagram of nMOS structure biased in onset of strong inversion (after
[1]). See List of symbols in Appendix 1 for definitions of EC, Ei, EF, EV, ΦS and ΦF.
The total capacitance of the MOS structure Ctotal now is a serial capacitance of the two
capacitors: oxide layer Coxide and inversion region in the semiconductor substrate CSi :
1
Ctotal

1
Coxide
Coxide  A

Coxide
1
CSi
 0 oxide
toxide
Dr. Radu Florescu
CSi 
C Si
q 0 Si N A
4 F
Dr. Vladislav Shteeman
9
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
(where  F  Ei(bulk )  EF  q is a built-in potential of the Si substrate (deep inside bulk); see
also List of definitions in Appendix 1)
Since the inversion layer is not built instantly, the inversion mode is time-dependent.
a.
At the equilibrium (slow sweep rate of V g and very low (20 – 200 Hz) frequency of the
b.
test signal or quasi-static conditions), the minority carriers have enough time to be
thermally generated in the depletion region and to follow the slow changes of the AC test
signal. Then they are drained to the oxide-semiconductor interface to form the inversion
layer. The inversion characteristic time is typically from 10ms to few seconds for silicon
depending on its doping. The total capacitance then rises to reach the oxide capacitance
value (low frequency capacitance, see Figure 7).
At the semi-equilibrium (slow sweep rate of V g and high frequency of the test signal,
c.
typically over 1-2 kHz), the inversion layer is still located at the oxide interface but cannot
follow the rapid changes of the AC test signal, since the thermal generation is slow. Then,
only the depletion layer can react by alternatively repelling and attracting the majority
carriers at its far-edge. Therefore, the total capacitance (at high frequency) is kept
constant to a minimum value, corresponding to the maximal extension of the depletion
layer at strong inversion.
At the non-equilibrium (high sweep rate of V g and high frequency of the test signal, kHz
and higher), the minority carriers have not enough time to build the inversion layer at the
oxide interface. Electron-hole pairs are generated too slowly to follow AC signal of
measurement. Therefore only the depletion layer should expand to balance the gate
charge variations. The total capacitance is then decreases below the minimum value
corresponding to the strong inversion. The capacitor is called to be in "deep depletion".
Dr. Radu Florescu
Dr. Vladislav Shteeman
10
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Figure 7. Low- and high- frequency capacitance of an nMOS capacitor. Shown are the exact
solution for the low frequency capacitance (solid line) and the low and high frequency
capacitance obtained with the simple model (dotted lines). NA = 1017 cm-3 and tox = 20 nm
(after [1]).
Dr. Radu Florescu
Dr. Vladislav Shteeman
11
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Experimental set-up
The experimental setup includes:
1. Shield probe station (including binocular microscope + CCD, moving table and micro manipulators),
connected (by the triax cables No 1, 2, 3, 4) to the Keithley matrix.
manipulator No 2
manipulator No 3
wafer TS510B
Figure 8. Shield probe station .
2. Agilent 4284A C-V analyzer.
Figure 9. Agilent 4284A C-V analyzer
See Appendix 2 for pin connections scheme for the MOS capacitors.
Dr. Radu Florescu
Dr. Vladislav Shteeman
12
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Assignments and analysis
Note: In the experiment, the total capacitance of the MOS capacitor is extracted from the measurements of
the impedance by the Agilent C-V analyzer, connected to the Keithley measurement system. The impedance
is defined as the ratio between the small AC test voltage signal (superposing the swept DC gate voltage V g )
and the measured AC current (at the top electrode):
Z 
V AC test probe
I AC measured
The two RC circuit models can be used to extract the capacitance: parallel and serial. In our case, the
resistance is mainly associated with the parallel BNC cables. Thus, the parallel model should be used (in
Keithley analyzer) for the measurements of MOS capacitor.
Measurements:
[1] Acquire C-V characteristics of MOS capacitor:
a. for the low frequency gate voltage V g (f = 100 Hz)
b. for the high frequency gate voltage V g (f = 1 MHz)
(See Appendix 2 and Appendix 3 for the details about pin connection, the range of gate voltage
and Keithley settings).
[2] (Optional) Acquire forward- and reverse measurements of C-V characteristics for MOS capacitor
(See Appendix 2 and Appendix 3 for the details about pin connection, the range of gate voltage
and Keithley settings).
Low frequency
High frequency
Figure 10. Typical C-V characteristics of nMOS capacitor (after [1]).
Dr. Radu Florescu
Dr. Vladislav Shteeman
13
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Note: after executing the measurements and before processing the acquired data, save this
Excel
nMOS Cap
processing.xlsx
template on your computer (double click on the Excel icon  File  Save as … ). Then copy the
results of the measurements (located in the measurements folder of Keithley in the subdirectory
“tests/data”), namely, data from the file “cp_mos#1@1.xls” to the Excel template, saved on your
computer.
Data processing and analysis:
The following parameters can be extracted from the C-V measurements of capacitor MOS:
Coxide
1. Oxide layer capacitance Coxide : the (averaged) saturation capacitance
in the “far” negative V g region:
2. Oxide
layer
toxide  A
thickness
 0 oxide
Coxide
toxide :
Coxide  A
since
 0 oxide
toxide

(where Coxide is known from the previous item and the capacitor area is



 

A  26175.4 m   26175.4  1012 m 2  26175.4  108 cm  )
2
2
Ctotal, LF
3. Oxide layer capacitance in the inversion region (both for low
frequency (LF) and high frequency (HF)), C Si, LF & C Si, HF . In the “far”
positive V g region, the total capacitance of capacitor MOS
gets
saturated. The C Si, LF & C Si, HF can be found from the (averaged)
Ctotal, HF
saturation capacitance:
1
Ctotal, LF
1
Ctotal, HF


1
Coxide
1
Coxide


1
CSi, LF
1
CSi, HF
Dr. Radu Florescu


1
CSi, LF
1
CSi, HF


1
Ctotal, LF
1
Ctotal, HF
Dr. Vladislav Shteeman


1
Coxide
1
Coxide
(CSi, LF is max)
(CSi, LF is min)
14
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
4. Threshold voltage Vth . The decrease of the total capacitance
slope in the depletion mode can be approximated by the linear
function. The intersection of this linear approximation with the
Vth
gate voltage V g axe is nothing but Vth .
5. Acceptors concentration in the Si substrate, N A :
NA 
2
2 oxide
0
VT
2
q Sitoxide  C
 oxide
C
 total, min
2

 1


OR
NA 
Ctotal
2
  1

 
2 
Ctotal  
q 0 Si A2  
 VG





VG
(The second formula should be used in the region of linear decrease of the total capacitance, as it
shown on the figure.)
(Pay attention: before substituting all the parameters in the formula above, you should convert them
into the System International (SI) units (namely, volts, farad, meters). Thus, the output N A value will be
3
in the units of m .)
6. Debye length LD :
LD 
 Si 0 kT
qN A q


where q  1.6  10 19 C  is the electron charge, for the room temperature T  27 C  300 K 
kT
 0.026 [V ] ,  Si  11.8 is the relative dielectric constant of Si
q
7. Built-in bulk potential of the Si substrate  F :
F 


kT N A
ln
q
ni
10
3
where ni  1.5  10 cm
is intrinsic carrier concentration for Si at the room temperature, and, as
before,
kT
 0.026 [V ] .
q
Dr. Radu Florescu
Dr. Vladislav Shteeman
15
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
8. Depletion layer width at the threshold voltage xd ,threshold (max possible depletion layer width):
xd ,threshold 
4 0 Si F
qN A
9. Flatband capacitance CFB . This is the total capacitance of the MOS structure under the flatband
condition S  0 (i.e. no charge exists in the semiconductor):
C FB 
1
1
Coxide

LD
 0 Si
CFB
10. Flatband voltage VFB . This is the voltage, corresponding on the C-V
graph to the flatband capacitance CFB .
11. Oxide Traps charge Qtraps . Consider hysteresis measurements of
V
FB
capacitor nMOS. (Same device is measured twice under the same
conditions. At “forward” pass the gate voltage slowly sweeps from negative to positive (i.e. from -3 to
+9 V). At “reverse” pass the gate voltage slowly sweeps from positive to negative (i.e. from +9 to -3 V)).
The CV characteristics at the two passes will be different in the depletion region and (almost) coincide
in the “far” negative (accumulation) and “far” positive (inversion) regions (see Figure 11). The difference
in the depletion region is due to the fact, that there are defects in the oxide substrate crystalline
structure. Those defects act like traps, confining electrons and thus changing the total capacity.
Dr. Radu Florescu
Dr. Vladislav Shteeman
16
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
VFB
blue – forward pass
red – reverse pass
Figure 11. Hysteresis measurements of nMOS capacitor. Dotted lines – linear
approximations of the total capacitance in different regions of the slopes.
Approximate the saturated capacity Coxide and the reducing capacitance in the depletion regions by the
linear functions (see Figure 11). The difference between the intersections of the linear forward (blue
dotted line) and reverse (red dotted line) decreasing lines with the horizontal line of the saturated
capacity (grey dotted line) gives us (in a good approximation) VFB - the difference in a flatband
voltage at the forward and the reverse passes. The total electric charge, confined in the traps, can be
estimated as follows:
Qtraps  Coxide  VFB
Final report must include the following information with explanations:
 
[1] The graph C Vg
[2] Oxide layer capacitance Coxide
[3] Oxide layer thickness toxide
[4] Capacitance of the Si capacitor in the inversion regime C Si
[5] Threshold voltage Vth
[6] Minimal capacitance of the Si substrate in the depletion regime, CSi,min
[7] Acceptors (nMOS) or donors (pMOS) concentration in the substrate, N A or N D
[8] Debye length LD
[9] Built-in bulk potential of the Si substrate  F
Dr. Radu Florescu
Dr. Vladislav Shteeman
17
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
[10] Depletion layer width at the threshold voltage xd ,threshold
[11] Flatband capacitance CFB
[12] Flatband voltage VFB
[13] (Optional) Oxide traps charge Qtraps
Dr. Radu Florescu
Dr. Vladislav Shteeman
18
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Acknowledgement
Department of Electrical and Electronic Engineering of Braude College would thank Mr. David Furman for
his extensive help and support in preparation of this laboratory work.
Several parts of this guide were adapted from the Capacitor MOS manual of the Advanced Semiconductor
Devices Lab (83-435) of School of Engineering of Bar-Ilan University. We would like to thank Dr. Abraham
Chelly for the granted manual.
Dr. Radu Florescu
Dr. Vladislav Shteeman
19
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Appendix 1 : List of symbols and definitions
List of symbols

 M - workfunction of the metal [Volt]
 Semiconductor - workfunction of semiconductor deeply inside the bulk [Volt]

 S  Ei( interface)  Ei( bulk ) - built-in surface potential at the interface between the semiconductor and

(interface)




(bulk )
oxide (SiO2) [Volt] . (Here, Ei
and Ei
are Fermi levels of the semiconductor at the interface
between the semiconductor and oxide (SiO2) and deeply inside the semiconductor bulk, respectively.)
 MS   M   Semiconductor - difference between the workfunctions metal and the semiconductor [Volt]
 F  Ei(bulk )  EF  q - built-in bulk potential of the Si substrate (deep inside bulk) [Volt]
N A , N D - acceptors (donors) average doping concentration (density) in the substrate [cm-3]
LD - Debye length (free path length of non-equilibrium minority carriers). Another interpretation of

Debye length – it is a characteristic length over which the carrier density in a semiconductor changes by
a factor e (~2.71)
A
capacitor
area
(for
our
devices,
both
for
nMOS
and
pMOS,
2
2
12
2
8
A  26175.4 m   26175.4  10 m  26175.4  10 cm  )

toxide - oxide layer’ thickness.


 oxide - SiO2 (silicon oxide) layer’ (relative) dielectric constant.  oxide  3.9
 Si - Si (relative) dielectric constant.  Si  11.8
 0 - permittivity of vacuum.  0  8.85 10-14 F cm  8.85 10-12 F m

Coxide - gate oxide capacitance: Coxide  A 0 oxide [ F ]

CSi - Si substrate capacitance. In the depletion mode, it is the capacitance of the depletion layer:










 
 

 
toxide
CSi 
q 0 Si N A
[ F ] . In the inversion mode, it is the capacitance of the inversion layer:
2 S
CSi 
q 0 Si N A
[F ] .
4 F
Cinv - capacitance of the inversion layer
CFB - flatband capacitance (total capacitance under condition: built-in potential at the semiconductor
surface  S  0 , in other words, no charge exists in the semiconductor).
V g - gate voltage [Volt]
VFB - flat band voltage [Volt]
Vth - threshold voltage [Volt]. When the gate voltage V g reaches some threshold, called Vth , an electron
channel is induced at the oxide-semiconductor interface. This happens at the onset of strong inversion,
when  S  2 F .

VFB - difference between the flatband voltages at the forward and the reverse passes at the hysteresis

measurements.
Qtraps - total electric charge, confined in the defects (traps) of the oxide substrate.
Dr. Radu Florescu
Dr. Vladislav Shteeman
20
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820

kT
, where kT is a thermal energy (i.e. energy, associated with the
q


temperature of the object, T ). For room temperature T  27 C  300 K  Vthermal  0.026 V
xd - width of depletion layer in semiconductor

xd ,threshold 

depletion layer width of the MOS capacitor
ni - intrinsic carrier concentration. For Si at the room temperature (T=300 K)  ni  1.5  1010 cm 3








Vthermal - thermal voltage. Vthermal 
4 0 Si F  qN A   2 0 Si S  qN A  -
depletion layer width at threshold, max


  8.617  105 eV
 - Boltzmann constant
k  1.38  1023  Joule
deg .K 

 deg .K 
T - temperature [deg. K]
q  1.6  10 19 C - electron charge
Ei - intrinsic Fermi level in semiconductor
Ei( interface) , Ei( bulk ) Fermi levels in semiconductor at the interface Si – SiO2 and deeply inside the bulk
E F - Fermi level in metal or in semiconductor at the given doping
E g , EC , EV - gap energy and energy of the bottom of the conduction band and the top of the valence
band in semiconductor
List of definitions
Bulk - Back contact of a MOS structure also referred to as the substrate contact.
Debye length LD - characteristic length over which the carrier density in a semiconductor changes by a factor e
(~2.71).
Depletion - removal of free carriers in a semiconductor
Flatband – is a bias condition of an MOS capacitor for which the energy band diagram of the device is flat (see Figure
3). The corresponding voltage is called the Flatband voltage, VFB . The flatband condition implies that no charge exists
in the semiconductor.
Flatband diagram – energy band diagram of a MOS capacitor containing no net charge in the semiconductor.
Flatband voltage VFB – a voltage, that must be applied the MOS structure to obtain the flat band diagram. The flat
band voltage is obtained when the applied gate voltage equals the workfunction difference between the gate metal
and the semiconductor: VFB   M   Semiconductor . If there is also a fixed charge in the oxide and/or at the oxide-silicon
interface, the expression for the flatband voltage must be modified accordingly.
Inversion - change of carrier type in a semiconductor obtained by applying an external voltage.
Inversion layer - the layer of free carriers of opposite type at the semiconductor-oxide interface of a MOS structure.




n+ (n-) semiconductor n-type semiconductor with high ( N D  1019 cm 3 ) and low ( N D  1016 cm 3 ) donor
density correspondingly.




p+ (p-) semiconductor p-type semiconductor with high ( N A  101 cm 3 ) and low ( N A  1016 cm 3 ) acceptor
density correspondingly.
Dr. Radu Florescu
Dr. Vladislav Shteeman
21
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Threshold voltage Vth – a gate voltage V g , corresponding to the point, when a channel (electron channel for
nMOS and hole channel for pMOS) is induced at the Si – SiO2 interface. This happens at the onset of strong
inversion, when  S  2 F . At the threshold voltage, depletion layer in Si reaches its maximum and does
not growths more with the gate voltage VG .
Work function of metal  M (semiconductor  Semiconductor ) - potential of an electron at the Fermi energy needs
to gain to escape from a solid.
Dr. Radu Florescu
Dr. Vladislav Shteeman
22
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Appendix 2: Wafer TS510B .
a. Wafer TS510B pin connections for nMOS device
Layout of the wafer’ checking area
Wafer appearance
checking areas
Note: here, it is NOT necessary to apply
an external voltage to the ground (pin 40
(19)) or Vcc (pin 26(5)) contacts.
checking area to be used
in our experiment
Pin connection
manipulator No 2
green lines
green lines
contact 26(5)
contact 25(4)
nMOS cap
Lo Pin contact - 26 (5)
Manipulator No 2
Hi Pin contact 25 (4)
Manipulator No 3
wafer serial TS510B
Dr. Radu Florescu
Dr. Vladislav Shteeman
manipulator No 3
23
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
b. Wafer TS510B – pin connections for pMOS device
Layout of the wafer’ checking area
Wafer appearance
checking areas
Note: here, it is NOT necessary to apply
an external voltage to the ground (pin 40
(19)) or Vcc (pin 26(5)) contacts.
Lo Pin contact 40 (19)
(ground) Manipulator No 2
wafer’ appearance :
5 checking areas
Pin connection
green lines
green lines
contact 24(3)
Hi Pin contact 24 (3)
Manipulator No 3
pMOS cap
wafer serial TS510B
Dr. Radu Florescu
Dr. Vladislav Shteeman
24
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Appendix 3 : Kite settings for C-V measurements of the
nMOS and pMOS capacitors.
a. pMOS device – high and low frequency
low frequency  f = 500 Hz
high frequency  f = 1 MHz
Expected results:
low frequency (f = 500 Hz)
high frequency (f = 1 MHz)
Dr. Radu Florescu
Dr. Vladislav Shteeman
25
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
b. nMOS device – C-V hysteresis curve
Forward pass (step +0.1 V)
Reverse pass (step -0.1 V)
Dr. Radu Florescu
Dr. Vladislav Shteeman
26
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Pay attention: in order to execute the reverse pass measurements, you must:
1.
2.
3.
change range from [-3V +9V] to [+9V -3V]
input negative step: -0.1 V (since you are swiping from positive +9 to negative -3 voltage)
run measurement by pressing the green-yellow button (which appends previous data) and not the green one
(which overwrites previous results).
Expected results:
Dr. Radu Florescu
Dr. Vladislav Shteeman
27
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Bibliography
1. B. Van Zeghbroeck, “Principles of semiconductor devices”, Lectures – Colorado University, 2004.
2. A. Chelly, “MOS-Capacitors”, Lab manual - Advanced Semiconductor Devices Lab (83-435),
School of Engineering of Bar-Ilan University.
3. B. Streetman, S. Banerjee, “Solid state electronic devices” (6th edition), Prentice Hall, 2005.
4. J. Singh, “Semiconductor devices: basic principles”, Whiley, 2001.
5. MOS capacitor simulator using Java Applet:
http://jas.eng.buffalo.edu/education/mos/mosCap/biasBand10.html
6. MOS capacitor calculator using Java Applet:
http://jas.eng.buffalo.edu/applets/education/mos/moscalc/index.html
Dr. Radu Florescu
Dr. Vladislav Shteeman
28
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Preparation Questions
1) Explain (in short) what is capacitor MOS.
2) What are the 3 main modes of capacitor MOS? Describe them in short.
3) What C-V characteristics do you expect for nMOS capacitor under the
i) high frequency measurements
ii) low frequency measurements
4) What C-V characteristics do you expect for pMOS capacitor under the
i) high frequency measurements
ii) low frequency measurements
5) How can you find (from the C-V characteristics) the following device’ parameters:
a.
Oxide layer capacitance Coxide
b.
Oxide layer thickness toxide
c.
Si depletion layer capacitance in the inversion region C Si
d.
Threshold voltage Vth
e.
Acceptors concentration in the substrate, N A
f.
Depletion layer width at the threshold voltage xd , threshold
g.
Flatband capacitance CFB
h.
Flatband voltage VFB
i.
Oxide traps charge Qtraps
Dr. Radu Florescu
Dr. Vladislav Shteeman
29