8. INVESTIGATION OF MOS STRUCTURES
8.1. Objective of the test
Analysis of physical processes at the surface of a semiconductor
and in metal-oxide-semiconductor (MOS) structures. Experimental
investigation of MOS structure capacitance versus bias voltage.
8.2. Theory and the main formulae
Surface conductivity of a MOS
structure is dependent on the
voltage applied to the structure (Fig
8.1(a)).
The structure can be considered
as a capacitor. The capacitance C of
the structure depends on the applied
0
U
(a)
voltage (Fig 8.1 (b)) and also is frequency dependent. Because of the
surface-charge layer in the semiC
conductor of the structure the
overall capacitance of a MOS
structure may be represented as a
capacitance C0 with oxide as a
0
(b)
U
dielectric material in series with the
Fig 8.1. (a) Surface conductivity space-charge layer capacitance C .
b
versus voltage and (b) capaUnder the condition of carrier
citance-voltage characteristic of a
accumulation there is no depletion
MOS structure
layer (Fig 8.2 (a)), and the overall
capacitance equals C0.
Beyond the strong inversion the maximum space-charge width
becomes constant (Fig 8.2 (c)). Then Cb and C are minimal and
constant.
σs
32
d
d
(a)
dn(U)
(b)
d
dn max
(c)
Fig 8.2. Models of the MOS structure
With biasing voltage between the condition of carrier accumulation and strong inversion, the width of the space-charge-layer is
dependent on the bias (Fig 8.2 (b)). The width increases with increase
of the bias voltage, causing decrease of the space-charge-layer capacitance Cb and overall capacitance of the structure. The capacitancevoltage characteristic shown in Fig 8.1(b) can be obtained experimentally if measurement frequency is high. The dashed line in Fig
8.1(b) shows the form of the characteristic at low frequency.
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1.
2.
3.
4.
8.3. Preparing for the test:
Using lecture-notes and referenced literature [1, p. 136–151],
examine surface phenomena in semiconductors, basic properties
of MOS structures and their applications. Clarify how the
capacitance of a MOS structure depends on the bias voltage.
Consider section “8.4. In laboratory” of this test.
Familiarise with the method of measurement of capacitance given
in section “7.6. Appendix” (previous laboratory test
“Investigation of pn junction capacitance”).
Prepare to answer the questions:
Name and discuss reasons of surface defects in semiconductors.
Explain the nature of non-mobile charges at the surface of a semiconductor and their influence on properties of a semiconductor.
Explain the nature of accumulation, depletion and inversion
layers at semiconductor surface.
Explain how the surface conditions can change properties of
semiconductor devices.
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5. Explain the essence of the field effect.
6. Explain how the conductance of the induced channel (inverse
layer) of a MOS structure depends on the bias voltage.
7. Name components of the total capacitance of a MOS structure
and explain their nature.
8. Explain the conditions for the accumulation layer to appear. What
determines MOS structure capacitance at accumulation?
9. At what conditions can a depletion layer appear in a MOS
structure? How and why does the capacitance of the structure
depend on biasing voltage at depletion conditions?
10. Explain the form of the capacitance-voltage characteristic of a
MOS structure after formation of the inversion layer.
11. Name possible applications of the field effect and MOS
structures.
8.4. In laboratory:
1. Answer the test question.
2. Familiarize with measurement devices and laboratory model.
3. Connect the measurement circuit shown in Fig 8.3.
Switch on a dc power source and set the voltage (+20V) as shown
in Fig 8.3. Switch on a harmonic wave generator and set up
100 kHz frequency and output voltage of 200 mV.
Fig 8.3. Circuit for MOS structure capacitance measurement
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After the teacher has checked the circuit, connect the dc power
source to the measurement circuit.
After any change do not switch the power source on before the
teacher has checked the connection!
During measurements voltage and current must not exceed the
highest values allowed for the used devices. In the case of this
laboratory test the voltage applied to a MOS structure must not
exceed Umax= 8 V.
4. Carry out necessary measurements, fill Table 8.1 and plot the
gradation curve.
Table 8.1. Measurement results of the gradation curve
Cg / pF
2.5
4
10
15
20
30
Uo / mV
5. Measure capacitance of a MOS structure used in the integrated
circuit (IC) K1LP721 changing bias voltage U. Lightly doped ntype silicon is used in the structure.
To this end before any measurement turn the control knob of
the potentiometer R1 counter-clockwise to the final position.
Connect one of MOS structures of the IC to the clamps Cx.
Note the values of output voltage Uo while changing the bias
voltage U applied to the structure from
–8 V to +8 V with
step of 0.5 V.
Do not change the position of laboratory model and connecting
cables during the measurements, then results of the measurements
will be more accurate.
Fill the column Uo in Table 8.2.
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Table 8.2. Measurement results
Ub
V
-8
-7.5
…
7.5
8
IC K1LP721
Uo / mV
CMOS / pF
Transistor KP305
Uo / mV
CMOS / pF
6. Find values of capacitance CMOS of the MOS structure
corresponding to U values using the gradation curve. Fill the
corresponding column in Table 8.2.
7. Measure capacitance of the MOS structure used for transistor
KP305 changing bias voltage U. Heavily doped n-type silicon is
used in the MOS structure of the transistor.
To this end connect the transistor to the clamps Cx. Note the
values of the output voltage Uo while changing the bias voltage U
from –5 V to +5 V with step of 0.5 V.
Fill the cells Uo and CMOS in Table 8.2.
8. Plot graphs CMOS(U).
9. Examine the results.
10. Prepare the report.
1.
2.
3.
4.
8.5. Contents of the report
Objectives.
Results of measurements in Tables 8.1 and 8.2.
Graphs: the gradation curve and graphs CMOS (U).
Conclusions. In this section explain shapes of the graphs CMOS(U).
Name and explain physical processes in investigated MOS
structures while changing the bias voltage.
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