How Fast Can You Design an Embedded System with SoC FPGAs?
Recently developed System-on-Chip (SoC) FPGAs featuring on-chip MCUs and associated
embedded peripherals, provide an impressive set of hardware resources with which to construct
embedded systems.
by Wendy Lockhart, Micosemi
A new generation of devices integrate a popular microprocessor architecture—most popularly an
ARM core—with its own extensive dedicated peripherals set, a large FPGA fabric with
dedicated SRAM blocks and math blocks, and dedicated external interfaces for high-speed serial
and high-speed parallel memory controllers.
SoC FPGA devices with these types of resources have complicated and interdependent designs
rules and use-models, which must be understood, in detail, to create a working solution. This
requires considerable work by an experienced FPGA designer to construct a system that is
capable of being used by the embedded programmer. As new peripheral features are required, the
FPGA designer must ‘spin’ the design to provide new features to the embedded programmer.
This dramatically extends the development cycle, and it requires that significant FPGA design
resources be applied to the project for the entire development cycle. What’s needed is a design
tool with a high-level of abstraction that intuitively captures the designer’s intent and then
generates correctly formed and connected designs.
Advanced Design Tool Requirements
The designer needs the ability to quickly and easily define the desired embedded components
and their interconnections. A visual, high-level abstraction for system construction that generates
a ‘correct by construction’ implementation will dramatically simplify the designer’s experience
and accelerate time to market. Using these tools, a traditional embedded system designer (one
with little FPGA hardware design experience) would be able to construct a complete SoC-based
embedded-system hardware platform using familiar embedded peripherals. These peripherals
could be implemented in fixed function MCU blocks, or in the FPGA fabric (using a library of
predefined FPGA-based IT building blocks). Once the system is thus defined, embedded code
can be rapidly developed.
An experienced FPGA designer would be required only when specialized functions, not already
available from the FPGA library, need to be added to the embedded system. Microsemi supports
these requirements with the System Builder GUI capability within the Libero SoC tool suite for
Microsemi SmartFusion2 SoC FPGAs. As an example, let’s review the hardware capabilities of
the SmartFusion2 SoC FPGAs, then we will explore the resulting requirements that drive the
preferred development flow.
The SmartFusion2 SoC FPGA is a mix of hard IP blocks and FPGA fabric on a single die. The
key elements include: the Microcontroller Subsystem or MSS, the FPGA fabric, the dedicated
external interfaces—high-speed serial and high-speed parallel memory, and the clock control
elements (Figure 1).
The MSS includes a high-speed ARM Cortex-M3 MCU with: an instruction cache, eNVM
program memory and eSRAM data memory, along with familiar peripherals like SPI, UART,
I2C, CAN, WDT, RTC, USB, external DDR memory controller, and Triple Speed Ethernet
(TSE) blocks. The MSS also has multiple interfaces to the FPGA to allow for peripheral
expansion and algorithm acceleration via custom peripherals and co-processing blocks within the
FPGA fabric. A high-speed external DDR interface is available to provide off-chip data for the
FPGA-based processing tasks. High-speed serial interfaces, with up to 165 Gbps SERDES, also
connect to the FPGA fabric and can operate in PCIe, XAUI/XGXS or native SERDES modes.
Finally, the clock control blocks include the System Clock, PLL, on-chip RC oscillators, and the
external crystal oscillator. Separate clock domains are available for the MSS, MDDR, MSS
APB, fabric interface, and the fabric DDR to simplify clock distribution.
SoC FPGA Embedded Development Key Features
To construct an easy to use embedded system development tool flow—one with which even an
MCU proficient but inexperienced FPGA designer would be comfortable—a few key features
need to be present. Supporting guided development of known good MCU subsystems is perhaps
the single most important capability required of the front-end development process. Let’s look at
how the System Builder wizard implements this key feature.
To simplify the development of a target SoC FPGA architecture (including MCU, peripherals,
memory interfaces, drives, peripherals/co-processors designed with FPGA fabric, etc.) the
System Builder wizard walks the architect through the steps of defining the elements of the
target system. The steps are organized by function, and only the features available, based on
previous selections, are presented as selections to the user. This dramatically simplifies the
process and creates a virtually error-free development environment. Two examples of System
Builder GUI screens are shown in Error! Reference source not found..
Some sample categories and example selections that can be used within the System Builder GUI
are listed below. Note that selection options are based on previous selections—thus this is a
‘guided’ approach:
Key Device Options: Select which memory features will be included in the design—MSS DDR,
fabric DDR, high-speed serial interfaces and flash memory storage clients.
Memory Options: Define the characteristics of the previously selected memory elements. For
example, specify the type of standard (DDR2, DDR3, LPDDR), the initialization time, and the
configuration options.
Peripheral Options: Define the characteristics of the available peripherals based on previous
selections. Selections are grouped by MSS master, MSS peripherals, fabric slave and fabric
master within which specific peripheral characteristics are selected.
MCU Options: Define the characteristics for microcontroller options, such as the Cortex-M3
processor, cache controller, AHB bus matrix, watchdog timer, real time counter, and peripheral
DMA controller.
Once all the configuration options have been defined, the System Builder wizard creates a
complete base system with IP blocks, associated device drivers and even includes relevant,
proven example code blocks, all correct by construction. This is possible because all the
configurable IP blocks have consistent hardware interfaces, common driver structures and
compatible software interfaces. The elimination of the requirement for an FPGA designer to
‘stitch together’ inconsistent interfaces ‘by hand’ dramatically reduces errors, and the need for
low-level verification and testing that can further extend development time. The System Builder
wizard also automatically includes proven example designs that show how to use the generated
blocks to further speed development. In many cases, the example designs require only minimal
changes to create application ready code.
Parallel FPGA and Application Development
Once the System Builder wizard has been run, the rest of the design flow is supported via the
Libero tool flow (Error! Reference source not found.) using familiar tools with no additional
learning curve for both the FPGA implementation and MCU application development. RTL and
constraints are made available for the FPGA implementation ‘leg’ of the development process,
while firmware and project settings are made available so embedded application development
can progress. Each effort can progress independently and when necessary FPGA developed
peripherals or acceleration co-processors can be easily imported into the embedded platform. For
example, the software developer might identify an ‘inner loop’ function that might be more
efficiently implemented in the FPGA fabric. The FPGA designer can construct the function in
the FPGA and then the programmer can use this co-processing hardware to replace the code,
dramatically improving the speed of the inner loop function. For the FPGA designer, the Libero
SoC integrates synthesis, debug and DSP support from Synopsys, and simulation from Mentor
Graphics with power analysis, timing analysis and push button design flow.
Using the Libero tool suite, embedded code development can be done via a familiar IDE, making
code development even more efficient. For example, Libero SoC allows the designer to use the
Keil Microcontroller Development Kit (MDK) or the IAR Embedded Workbench IDE. Because
the SmartFusion2 SoC uses an ARM Cortex-M3 processor core and many standard ARM
peripherals, previous development efforts can easily be leveraged to further speed the
development cycle. Microsemi also supplies an Eclipse-based IDE, SoftConsole, with a GNU
C/C++ compiler and GDB debugger.
The SmartFusion2 development environment includes higher-level software elements to make it
easy for application developers to immediately use the underlying software layers. Error!
Reference source not found. shows the software stack for a typical design and illustrates how
various elements fit into the software hierarchy. The bottom layer is the actual hardware
associated with the device and includes all the hardware components of the system. The next
layer up is the Hardware Abstract Layer (HAL), which is based on the ARM Cortex
Microcontroller Software Interface Standard (CMSIS). Each of the peripherals has its own
driver, whether it is hard IP or soft IP added in the FPGA fabric. Above the drivers, is a real-time
operating system (RTOS) with protocol Guided Development and the System Builder GUI
stacks and interfaces, provided by third party vendors. At the top layer, the designer can add their
own ‘secret sauce’ or custom applications involving all or none of the layers below. he use of an
ARM processor allows designers to benefit from the extensive ARM ecosystem, established
HAL and drivers. This also allows third party vendors to easily port RTOS and middleware for
SmartFusion2 devices.
All device drivers and peripheral initialization are auto-generated and correct by construction via
the System Builder GUI selections. Devices are programmed and debugged via the Flashpro 4
programmer.
Because the System Builder GUI automatically provides drivers for SmartFusion2 peripherals,
software development can focus on the differentiated features required by the target market. For
example, an application developer can take the System Builder GUI output and immediately
integrate an OS/RTOS along with the associated Middleware for a TCP/IP stack. Within minutes
the design can be compiled, programmed and run so that it can exchange messages over an
Ethernet network. This is a dramatic improvement over previous design flows where days and
weeks of development, testing and debugging were required to get all the elements of the
hardware and software working together to create a simple working Ethernet-enabled design.
The advanced capabilities of SoC FPGAs require accompanying advances in the tool flow for
designers to reap the enormous benefits of using these devices. A high-level system constructor,
like the System Builder GUI, uses a guided design approach to quickly create a, correct by
construction, base system that encapsulates everything needed so that the development tasks of
coding for the embedded MCU and coding for the FPGA fabric can be done independently.
Additionally, by incorporating all the key software elements (the hardware abstraction layer,
drivers, and even example code) into the base system, MCU application development can begin
immediately, without the multitude of preliminary time consuming steps required in less
integrated flows. This significantly reduces the potential for false steps and development
backtracking that previously plagued complex SoC designs.
Microsemi, Aliso Viejo, CA. (949) 380-61--. [www.microsemi.com]