Lecture 6: CMOS Logic Circuits In this lecture, we move down a level in the design hierarchy to provide a basic introduction to the transistor circuitry that is used to build the logic gates we have been working with. In particular, we will see the motivation for using NAND or NOR gates instead of AND or OR gates, and we will also see how to configure a CMOS circuit to implement a Boolean equation directly. Learning Outcomes: On completing this lecture, you will be able to describe the operation of a MOS transistor in ideal switch terms; sketch the circuit diagram and explain the operation of a CMOS inverter, NAND gate, and NOR gate; analyse and configure single-gate CMOS logic structures. 6.1 Introduction Today’s integrated circuits are virtually exclusively based on what is known as CMOS circuit technology. The designation MOS denotes a particular type of field effect transistor called a Metal Oxide Semiconductor (MOS) device. There are two such devices: one device, in which the electrical current is carried by electrons, is termed an n-channel transistor; the other device, in which the electrical current is transported by “holes” or mobile positive charge centres, is termed a p-channel transistor. When these two devices are combined in a particular circuit configuration, we have what is called Complementary MOS circuit technology or CMOS. Digital CMOS integrated circuits today, such as the Intel Core 2 Duo, comprise up to 400 x 106 transistors on a single silicon crystal. Device feature sizes, which determine the area occupied by a minimum-sized transistor, are as small as 45nm (m x 10-9). Among the many advantages of CMOS circuit technology are: Very good to excellent electrical performance (voltage levels, speed, power) Manufacturability Reliability Availability of CAD tools Availability of already-designed complex building blocks A recurring theme in the research literature is the question: what are the ultimate limits of silicon technology? The experience thus far has been that, as soon as any practical limit is set, it is only a matter of time until the integrated circuit fabrication industry reaches and exceeds that limit. The most likely limit could arise from manufacturing economics, as the costs of producing the new generations of manufacturing equipment are rising faster than the minimum feature size is shrinking. 6.2 Transistor Operation It is not proposed here to delve into the semiconductor details of the device but rather to simply outline the electrical properties of the device as seen from its nodes and when operated in a digital manner, ie with either a high voltage VH or a low voltage VL as controlling input. 6-1 The n-Channel Transistor D D VG = VL G S D VG = VH S S This device has three electrical nodes, termed the gate G, the drain D, and the source S. The gate may be regarded as a controlling node, determining the electrical properties of the channel between the drain and source. When operated digitally, ie by VH or VL applied to G, the channel between the D and S nodes behaves like an ideal switch, controlled by the voltage VG applied to the gate. As shown in the diagram: If VG = VH, then D is essentially connected to S and we say the switch is closed; If VG = VL, then there is no connection between D and S, and we say the switch is open. The p-Channel Transistor S S G VG = VL S VG = VH D D D This device again has gate G, source S, and drain D nodes in this instance we depict the S node above the D node because it would be normal to find a higher potential on the source than on the drain; the opposite would be the case for the n-channel transistor. The device functions similarly to the n-channel except that the role of the gate is inverted: If VG = VH, then there is no connection between S and D, and we say the switch is open; If VG = VL, then D is connected directly to S, and we say the switch is closed. 6.3 The CMOS Inverter Consider the circuit shown in the diagram over. It comprises of just two MOS transistors, one n-channel device and one p-channel device. The two gates are interconnected and together form the input to the circuit Vi. Similarly, the two drain nodes are interconnected and form the circuit output voltage Vo. The circuit is supplied with a high voltage VH which is connected to the source of the p-channel transistor while a low voltage VL is supplied to the source of the n-channel transistor; VH/VL are derived from a dc voltage source, not shown. Note the highly structured configuration; this is what makes CMOS circuits particularly easy to configure using CAD techniques. To determine how the circuit operates digitally, we consider just two possible values of input voltage, VH and VL. For each of these input voltages we simply model the transistors by means of switches as previously described; essentially we replace each transistor by an appropriate open or closed switch depending on the input voltage and the transistor type. 6-2 If Vi = VL, then the n-channel device is replaced by an open switch while the p-channel device is replaced by a closed switch. The result is that the output voltage gets connected to the VH supply (and disconnected from the VL supply). VH VIN VH VOUT VL VH VIN = VL VOUT = VH VIN = VH VL VOUT = VL VL If Vi = VH, then the n-channel device is replaced by a closed switch while the p-channel device is replace by an open switch. The result now is that the output gets connected through to VL (and disconnected from VH). Thus the overall operation may be summarised by the voltage truth table Vi VL VH Vo VH VL which is easily recognised as that of the inverter. Note that the basic idea of the circuit is that the output node gets connected to either V H or VL depending on the particular value of the input voltage. Note also that, irrespective of what state the circuit is in (Vo high or low), no current flows from VH through the two transistors to VL because one or other of the two transistors will be like an open switch thus breaking the current path. This feature is the basis for the low power demand of CMOS logic circuits. 6.4 The CMOS NAND and NOR Gates Consider the CMOS logic circuit shown in the diagram over. The circuit comprises two pchannel transistors in parallel and two n-channel transistors in series. The circuit has two logic inputs, A and B. A is connected to the gate of one n-channel transistor and to the gate of one p-channel transistor. Similarly input B is connected to one n-channel and to one pchannel device. Also note that between the output X and the high voltage VH is the network of p-channels, while between the output X and the low voltage VL is the network of nchannels. For reasons beyond the scope of this course, in a correctly configured CMOS logic circuit, one does not place n-channel devices between an output node and VH; nor does one place p-channel devices between the output node and VL. Accompanying the electric circuit diagram is a switch representation or model; in this diagram the switches are simply depicted without reference to particular input conditions. Nevertheless, the same general rules as described previously hold: for a high input voltage, the corresponding n-switch is closed while the p-switch is open. For a low input voltage, the corresponding n-switch is open while the p-switch is closed. Based on these considerations, 6-3 the following table lists the states of all four switches for the four possible input combinations. VH A VH SPA B SPB X X A SNA B SNB VL A 0 0 1 1 B 0 1 0 1 VL SPA closed closed open open SPB closed open closed open SNA open open closed closed SNB open closed open closed X 1 1 1 0 To determine the values of the output X, we note from examination of either diagram that X is at VH if either SPA or SPB is closed X is at VL if both SNA and SNB are closed. Applying these two rules we arrive at the column for output X given in the table. We note that the truth table for X corresponds to the NOT-AND function, ie NAND. Hence the circuit is that of a two-input NAND gate. It should be clear that a three-input NAND gate can be configured by adding one further pchannel device in the upper half of the circuit and one further n-channel in the lower series connected network and so on for a four input gate, etc. Consider now the following CMOS logic circuit. VH VH A SPA B SPB X A X B SNA VL SNB VL 6-4 Note the reciprocal arrangement compared to the previous circuit; the two p-channel transistors are now in series whereas the two n-channel devices are in parallel. All the transistors do, however, obey the same rules as above with regard to the switch being open or closed. Consequently, the switch part of the truth table, below, is precisely the same as previous. A 0 0 1 1 B 0 1 0 1 SPA closed closed open open SPB closed open closed open SNA open open closed closed SNB open closed open closed X 1 0 0 0 Observing the circuit diagram, we note X = VH if SPA is closed and SPB is closed X= VL if SNA is closed or SNB is closed Hence we arrive at the given listing of values for X which we note correspond to those of the NOR function. Thus the circuit is that of a CMOS NOR gate. The above two configurations, together with the earlier one for the inverter, constitute the basic set of most simple CMOS logic circuits. Clearly, to realise an AND function, we must follow a NAND gate with an inverter it is simply not possible to configure an AND gate using just a sub-network of n-channel transistors and a sub-network of p-channel devices. It is as if the CMOS architecture has a built-in overall inverting function. 6.5 More Complex CMOS Logic Consider the following CMOS logic circuit and the corresponding switch-based model. VH A B A' B' VH SPA SPA' SPB SPB' X X A A' SNA SNA' B B' SNB SNB' VL VL 6-5 We can make the following statements regarding the output X: X=1 if [A=0 or B=0] and [A=0 or B=0] X=0 if [A=1 and B=1] or [A=1 and B=1] From these statements, the following truth table is generated: A 0 0 1 1 B 0 1 0 1 X 0 1 1 0 which in turn leads to the Boolean equation X AB AB and which is recognised as being the Exclusive-OR function. In other words, the above circuit diagram represents in transistor form an Exclusive-Or gate, demonstrating that the Exclusive-OR can be built with eight transistors and should have a propagation delay somewhat the same as that for a two-input NAND or NOR gate. Alternatively, by focussing on the 0’s of the truth table, the Boolean function could be specified as X AB AB which might be more in line with the previously mentioned property of CMOS as having a built-in overall inverting function. However, the two equations are equivalent. 6.6 Conclusion In this lecture, we have explained in switch terms the operation of MOS transistors and shown how a combination of n-channel and p-channel devices can be configured to implement logic functions, both basic such as NAND and NOR and more complex such as the Exclusive-OR. This so-called CMOS architecture comprises a network of p-channel devices between the output and the VH supply and a network of n-channel devices between the output and the VL supply. 6-6