Silicon Labs Programmable Product Request Form
Please complete the below information return via email to PPR@silabs.com.
Applicable parts: Si5121x: Tiny Clock; Si5213x: Programmable PCIe clocks; Si54090/Si54091: 4PLL with OTP (consider using Si5350 instead); SL15300: 1PLL with EEPROM (consider using Tiny Clock
instead); SL38000: 4PLL (consider using Si5350 instead); SL28PCIexx: Programmable PCIe clock (consider using Si5315x instead).
Category
Category
Date
SiLabs Sales Person
Target part for customization
Alternate part (if applicable)
Customer Company Name
Targeted application
Volume in K/year
Target price
Required sample date
Required sample quantities
Mass production date
Product lifecycle
Current solution and / or
competitive part number
Required temp range
Please complete table1. If items are left unspecified, it is assumed customer does not need the item, or can accept any variable (e.g., xtal input frequency). Attach block diagram if available.
Input /
Target SOC
Target Center
Output type and
Spread
fTOL
fACC
VDD Typ.
CCJ
Other Key Parameters / Comments
Output
Application
Freq (MHz)
Voltage
%
(± ppm)
(± ppm)
(V)
CLK1
Example: Wi-Fi
Example: 40MHz
Example: LVCMOS
CLK2
CLK3
REFCK1
Xin / Xout
Example: VCXO pull range (+/-ppm): _____
Example: Xtal CL; CL(pF): ____
Crystal input
Clock in
External clock
1 – Column Field Definitions:
Input / Output type and Voltage: Required output type with specified swing level (e.g. 1.8V LVCMOS, 2.5V LVCMOS, 3.3V LVCMOS, HCSL/PCIe, etc.).
Spread: If spread spectrum EMI reduction is required, list all desired spread options (e.g. -0.5%, +/-0.25%, -1%, +/-0.5%).
CCJ: The cycle to cycle jitter requirements for 10,000 clock periods CCJ = Absval(+/-CCJ). (list Max and NOTE THE UNITS (s / ns / ps).
FTOL: Frequency tolerance at 25C requirement excluding crystal error (total allowable output error (ppm) - crystal spec (ppm)) (e.g. (+/-50) – (+/-30) = +/-20).
FACC: Frequency accuracy across temp requirement excluding crystal error (total allowable output error (ppm) - crystal spec (ppm)) (e.g. (+/-50) – (+/-30) = +/-20).
VDD Typ: Typical power supply spec for this output. Generally this is the same for all outputs unless some are running on separate VDD planes.
Other Key Parameters/Comments: List any of the following if applicable:
1. LTJ/Dly/Acq
a. LTJ: Long Term Jitter requirements (e.g., 800pS) [LTJ = max – min, of accumulated jitter].
b. Dly: Time delay setting for measurement (e.g., 10s).
c. Acq: Number of acquisitions to be measured (e.g., 1000).
2. Duty Cycle: The duty cycle limits (e.g. 45%-55%).
3. Tr/Tf: Rise and fall times measured at 20%-80% of VDD, specify whether min, max or typ.
4. CL: For output clocks this is the total load capacitance driven by the output and includes estimated trace capacitance and the receiver input capacitance. If the I/O signal is Xin/Xout,
then CL refers to the load capacitance of the crystal taken from the crystal datasheet.
5. VCXO: If applicable, enter desired pull range and crystal parameter C0/C1 (to determine if crystal is pull-able).
www.silabs.com
rev. 3.0