Dld
(DIGITAL LOGIC DEISGN)
ASSIGNMENT NO . 2:
FINITE STATE MACHINE
&
MOORE MACHINE
 SUBMITTED BY:
GROUP B
 SUBMITTED TO:
DR. ZAKI
1
(KAHUTA INSTITUTE OF COMPUTER SCEINCE &
INFORMATION TECHNOLOGY)
Quotation
Attain knowledge before old age settles in
-Hazrat Umer Farooq (R.A)
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GROUP MEMBERS
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Umer Farooq
Muhammad Rizwan
SM Abdur Rehman
Waleed Iqbal
Uzair Qureshi
Zeeshan Rafique
Faiser Mehmood
Faisal Ashfaq
Bilal Khan
Muhammad Usman
Syed Hassan Manzoor
Ali Salman
Asad Raza
Sheraz Mehfooz
Junaid Asghar
Jawad Mohaiudin
Zaigham Raza
Muhammd Adeel
Usman Wahid
Umar Nawaz Abbasi
Agha Rehan Ali
Usama Saeed
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 Finite-state machine:
A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply
a state machine, is a mathematical model of computation used to design
both computer programs and sequential logic circuits. It is conceived as an abstract
machine that can be in one of a finite number of states. The machine is in only one state
at a time; the state it is in at any given time is called the current state. It can change
from one state to another when initiated by a triggering event or condition, this is called
a transition. A particular FSM is defined by a list of its states, and the triggering
condition for each transition.
The behavior of state machines can be observed in many devices in modern society
which perform a predetermined sequence of actions depending on a sequence of
events they are presented with. Simple examples are vending machines which dispense
products when the proper combination of coins are deposited, elevators which drop
riders off at upper floors before going down, traffic lights which change sequence when
cars are waiting, and combination locks which require the input of combination numbers
in the proper order.
Finite-state machines can model a large number of problems, among which
are electronic design automation, communication protocol design, language parsing and
other engineering applications. In biology and artificial intelligence research, state
machines or hierarchies of state machines have been used to describe neurological
systems and in linguistics—to describe the grammars of natural languages.
Considered as an abstract model of computation, the finite state machine is weak; it has
less computational power than some other models of computation such as the Turing
machine.[1] That is, there are tasks which no FSM can do but a Turing machine can do.
This is because the FSM has limited memory. The memory is limited by the number of
states.
 Advantages and Disadvantages of FSM
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 Advantages of FSM:
1. Their simplicity make it easy for inexperienced developers to implement
with little to no extra knowledge (low entry level).
2. Predictability (in deterministic FSM), given a set of inputs and a known
current state, the state transition can be predicted, allowing for easy
testing
3. Due to their simplicity, FSMs are quick to design, quick to implement and
quick in execution
4. FSM is an old knowledge representation and system modeling technique,
and its been around for a long time, as such it is well proven even as an
artificial intelligence technique, with lots of examples to learn from
5. FSMs are relatively flexible. There are a number of ways to implement a
FSM based system in terms of topology, and it is easy to incorporate
many other techniques
6. Easy to transfer from a meaningful abstract representation to a coded
implementation
7. Low processor overhead; well suited to domains where execution time is
shared between modules or subsystems. Only the code for the current
state need be executed, and perhaps a small amount of logic to determine
the current state.
8. Easy determination of reachability of a state, when represented in an
abstract form, it is immediately obvious whether a state is achievable from
another state, and what is required to achieve the state
 Disadvantages of FSM:
1. The predictable nature of deterministic FSMs can be unwanted in some
domains such as computer games (solution may be non-deterministic
FSM).
2. Larger systems implemented using a FSM can be difficult to manage and
maintain without a well thought out design. The state transitions can cause
a fair degree of "spaghetti- factor" when trying to follow the line of
execution
3. Not suited to all problem domains, should only be used when a systems
behavior can be decomposed into separate states with well defined
conditions for state transitions. This means that all states, transitions and
conditions need to be known up front and be well defined
4. The conditions for state transitions are ridged, meaning they are fixed (this
can be over come by using a Fuzzy State Machine (FuSM))
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Uses:
State Machines are a rather abstract concept if you’re not used to dealing with them. They
have their roots in mathematics (where we also find Non-Finite State Machines, but we won’t
be going into those here).
So what are State Machines used for? In the programming world, generally speaking, State
Machines are useful when you read input and what you have to do with that input depends on
things previously encountered in the input.
In practice, State Machines are often used for:
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Design purposes (modeling the different actions in a program)
Natural language (grammar) parsers
String parsing
Algorithms
And many other things
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Theory:
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Basic properties:
State Machines exhibit some basic properties. Not every type of State Machine has all of
them, but they always have at least one of them:
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Input. State Machines have input. These are usually called symbols.
States. For example: lightswitch=on, heatsensor=off, etc.
Transitions. When the State Machines changes its state, this is called a transition. A
transition usually requires a condition, The condition is determined by the input, the
current state or a combination of both.
Actions. An Action is a rather generic description for anything that can happen in a State
Machine. Actions may be performed when entering or exiting a state, when input is read,
when a state transition occurs, etc.
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Types of State Machines:
There are two types or Finite-State Machines which are typically used in computer programs:
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Acceptors / Recognisers
Transducers
The Acceptors/Recognisers read bits of input and in the end tell you only if the input was
accepted or not. One example would be a State Machine that scans a string to see if it has the
right syntax. Dutch ZIP codes for instance are formatted as "1234 AB". The first part may
only contain numbers, the second only letters. A State Machine could be written that keeps
track of whether it’s in the NUMBER state or in the LETTER state and if it encounters wrong
input, reject it.
Transducer on the other hand continuously read pieces of input and for each piece of input
produce either some output or nothing. What it produces can depend on the input and the
current state of the machine. A good example of this is a string parser that allows the user to
enclose a part of the string in quotes so that it is treated as a single item. On the Unix shell
this is used to refer to file names with a space in them. The State Machine reads one character
at a time. When a space is read, it assumes a new element is starting. If it encounters a quote,
it enters the QUOTED state. Any characters read while in the QUOTED state are assumed to
be part of the same element. When another quote is encountered, the State Machine
transitions to the UNQUOTED state.
 Model of finite state machine (FSM):
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 State diagram of finite state machine (FSM):
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Controlling sequence diagram of finite state machine:
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 TRANSITION STATE DIAGRAM OF FINITE STATE
MACHINE (FSM):
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 Schematic diagram of finite state machine:
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Example of finite state machine (FSM):
 A Modulo-4 Synchronous Counter:
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Counts from 0 to 3 and then repeats.
It has a clock input (CLK) and a RESET input.
Outputs appear as a sequence of values (q1 and q0) at time steps corresponding
to the clock.
As the outputs are generated, a new state (s1s0) is generated which takes on
values of 00, 01, 10, and 11 and are fed back to the input.
The Mod-4 Counter:
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Requires four states, encoded in binary, with at least two bits for them to be
encoded uniquely.
▫ A = 00
▫ B = 01
▫ C = 10
▫ D = 11
The input requires only a single bit.
▫ 0|1
State Transition Diagram for the Mod-4 Counter:
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 State Table for the Mod-4 Counter:
 State Assignment for the Mod-4 Counter:
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 Truth Table for the Mod-4 Counter:
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 Logic Design for Mod-4 Counter:
 Types of finite state machines:
There are the two types of finitestate machines (FSM)
1. Mealy machine:
In the theory of computation, a Mealy machine is a finite-state machine whose
output values are determined both by its current state and the current inputs.
(This is in contrast to a Moore machine, whose output values are determined
solely by its current state.)
2. Moore machine:
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In the theory of computation, a Moore machine is a finite-state machine whose
output values are determined solely by its current state. This is in contrast to
a Mealy machine, whose output values are determined both by its current state
and by the values of its inputs. The Moore machine is named after Edward F.
Moore, who presented the concept in a 1956 paper, “Gedanken-experiments on
Sequential Machines.
 MOORE MACHINE:
A Moore machine is a finite-state machine whose output values are determined solely by its
current state. This is in contrast to a Mealy machine, whose output values are determined both
by its current state and by the values of its inputs.
HISTORY:
The Moore machine is named after Edward F. Moore, who presented the concept in a 1956
paper, “Gedanken-experiments on Sequential Machines.
Formal Definition:
A Moore machine can be defined as a 6-tuple ( S, S0, Σ, Λ, T, G ) consisting of the following:
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a finite set of states ( S )
a start state (also called initial state) S0 which is an element of (S)
a finite set called the input alphabet ( Σ )
a finite set called the output alphabet ( Λ )
a transition function (T : S × Σ → S) mapping a state and the input alphabet to the next state
an output function (G : S → Λ) mapping each state to the output alphabet
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 FUNCTIONL BLOCK DIAGRAM OF MOORE
MACHINE:
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 TIMING DIAGRAM OF MOORE MACHINE:
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 Applications of Moore machine:
1. First example of Moore Machine:
Figure below is a diagram of a simple Moore finite-state machine. It has one input (X), four
internal states (S0 to S3), andone output (Z).
The VHDL code implementing this finite-state machine is shown in example below,
which includes a schematic of the synthesized circuit.The machine is described with
twoprocesses. One processdefines the synchronous elements of the design
(stateregisters);the other process defines the combinational part of the design (state
assignment case statement)..
Example of Implementation of a Moore Machine
entity MOORE is –– Moore machine
port(X, CLOCK: in BIT;
Z: out BIT);
end;
architecture BEHAVIOR of MOORE is
type STATE_TYPE is (S0, S1, S2, S3);
signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;
begin
–– Process to hold combinational logic
COMBIN: process(CURRENT_STATE, X)
begin
case CURRENT_STATE is
when S0 =>
Z <= ’0’;
if X = ’0’ then
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NEXT_STATE <= S0;
else
NEXT_STATE <= S2;
end if;
when S1 =>
Z <= ’1’;
if X = ’0’ then
NEXT_STATE <= S0;
else
NEXT_STATE <= S2;
end if;
when S2 =>
Z <= ’1’;
if X = ’0’ then
NEXT_STATE <= S2;
else
NEXT_STATE <= S3;
end if;
when S3 =>
Z <= ’0’;
if X = ’0’ then
NEXT_STATE <= S3;
else
NEXT_STATE <= S1;
end if;
end case;
end process;
–– Process to hold synchronous elements (flip–flops)
SYNCH: process
begin
wait until CLOCK’event and CLOCK = ’1’;
CURRENT_STATE <= NEXT_STATE;
end process;
end BEHAVIOR;
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2. Second example of Moore Machine:
Finite State Machines with Output of Moore Machine:
 Introduction:
If a combinational logic circuit is an implementation of a Boolean function, then a sequential
logic circuit can be considered an implementation of a finite state machine. There is a little
more to it than that (because a sequential logic circuit can contain combinational logic circuits).
If you take a course in programming languages, you will also learn about finite state machines.
Usually, you will call it a DFA (deterministic finite automata).
While finite state machines with outputs are essentially DFAs, the purpose behind them is
different.
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 DFAs in programming languages:
When you are learning about models of computation, one simple model is a deterministic finite
automata or DFA for short.
Formally, the definition of a DFA is:
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Q, a set of states
S, an single state which is an element of Q. This is the start state.
F, a set of states designated as the final states
Sigma, the input alphabet
delta, a transition function that maps a state and a letter from the input alphabet, to a
state
DFAs are used to recognize a language, L. A language is a set of strings made from characters in
the input alphabet. If a language can be recognized by a DFA, it is said to have a regular
grammar.
To use a DFA, you start in an initial state, and process the input string a character at a time. For
example, if the input alphabet consists of "a" and "b", then a typical question is to ask whether
the string "aaab" is accepted by a DFA.
To find out whether it is accepted, you start off in the state S. Then you process each character
(first "a", then "a", then "a", and finally "b"). This may cause you to move from one state to
another. After the last character is processed, if you are in a final state, then the string is in the
language. Otherwise, it's not in the language.
There are some languages that can't be recognized by a DFA (for example, palindromes). Thus, a
DFA, while reasonably powerful, there are other (mathematical) machines that are more
powerful.
Often, tokens in programming languages can be described using a regular grammar.
 FSM with output in hardware:
A finite state machine with output is similar to describe formally.
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Q, a set of states
S, an single state which is an element of Q. This is the start state.
Sigma, the input alphabet
Pi, the output alphabet
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
delta, a transition function that maps a state and a letter from the input alphabet, to a
state and a letter from the output alphabet.
The primary difference is that there is no set of final states, and that the transition function not
only puts you in a new state, but also generates an output symbol.
The goal of this kind of FSM is not accepting or rejecting strings, but generating a set of outputs
given a set of inputs. Recall that a black box takes in inputs, processes, and generates outputs.
FSMs are one way of describing how the inputs are being processed, based on the
inputs and state, to generate outputs. Thus, we're very interested in what output is generated.
In DFAs, we don't care what output is generated. We care only whether a string has been
accepted by the DFA or not.
Since we're talking about circuits, the input alphabet is going to be the set of k bit bitstrings,
while the output alphabet is the set of m bit bitstrings.
We'll look at this more informally, just in case you're confused.
Each of the circle is a state. For now, all you need to know is that, at any given moment, you are
in one state. Think of this as a game, where there are circles drawn on the ground, and at any
moment, you are standing in exactly one circle.
Each of the circle is given a unique binary number. The number of bits used depends on the total
number of states. If there are N states, then you need ceil( lg N ) bits (the ceiling of log base 2 of
N). The states are labelled with the letter q, plus subscripts. In this example, it's q1q0.
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You may have k input bits. The input bits tell you which state to transition to. For example, if
you have 2 input bits (x1x0), then there are four possible out going edges
(x1x0 = 00, x1x0 = 01, x1x0 = 10, and x1x0 = 11). In general, there are 2k outgoing edges for k bits
of input.
Thus, the number of edges depends on the number of bits used in the input.
 Tracing an Example:
You might be asked, what are the sequence of states and outputs, assuming you start in state
00, and have input (1, 1, 0, 0, 1).
State 00 (Start) 01 10 01 01 10
Input
1
1
0
0
1
So, you may start in state 00, reading input 1 (see column 1 of the table), which puts you in state
01. At that point, you read in input 1 (see column 2), and go into state 10 (column 3), etc.
 FSM with Outputs: Moore machines
The goal of FSMs is to describe a circuit with inputs and outputs. So far, we have inputs, that tell
us which state we should go to, given some initial, start state. However, the machine generates
no outputs.
We modify the FSM shown above, by adding outputs. Moore machines add outputs to each state.
Thus, each state is associated with an output. When you transition into the state, the output
corresponding to the state is produced. The information in the state is typically written as 01/1.
01 indicates the state, while 1 indicates the output. 01/1 is short hand for q1q0 = 01/z = 1
The number of bits in the output is arbitary, and depends on whatever your application needs.
Thus, the number of bits may be less than, equal, or greater than the number of bits used to
represent the state.
Let's look at an example of a Moore machine.
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In this example, you see two bits for the state and two bits for the output. Thus, when you see
00/01 inside one of the circles, it is shorthand for q1q0 = 00 / z1 z0 = 01.
 Tracing using Timing Diagrams:
Given the Moore machine in the previous diagram, and the timing diagram below, you might be
asked to determine the state and output.
The timing diagram isn't too hard to follow. Basically, you will start off in some state (let's say,
00), and draw the diagram to indicate what happens to the state (q1q0) and to the output (z1z0).
You'll notice the input does NOT change at the positive edge. That way, it's easier for you to tell
the value of the input at the positive edge. To make it easier to read, I've added the value of x at
the positive edge. Thus, the inputs are 1, 1, 0, 1, 1, 0.
Let's look at the timing diagram at the first positive edge (drawn with a vertical line). Before the
first edge, the state, q1q0 = 00. The input is 1. This should put us in state 01 (i.e., q1q0 = 00),
which outputs 11 (i.e., z1z0 = 11).
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You have to read down the columns. The first column says that the machine is in state 00, with
output 01. The second column says that the machine is in state 01, with output 11. The reason the
second column says that is due to the input, x, read in at the first positive edge. The input x is 1,
which caused the FSM to move from state 00 to state 01.
The value of the state and output are placed in the middle, but the really, it's the dark line that
tells you when this happens. The state and output changes value on the positive edge
(technically, it takes a small, but finite amount of time after the positive edge for the state and
output to finally settle down, but we'll draw the diagrams as if it happens instantaneously---even
though it doesn't).
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Here's the rest of the timing diagram.
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3. Third example of Moore Machine:
F1 is B<= not (A and C)
F2 is D<= not C
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Output is a function of the state registers.
The simplest Moore machine use only one process , see next page
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Moore machine example:
1.Architecture moore2_arch of system is
2. Signal C: bit; -- global, can be seen by different
3 begin
4. Since D is purely for output, no feedback read
5 -- requirement, so it has the type out
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D<= not C; -- F2 = combination logic
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process
-- sequential logic
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begin
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wait until clock;
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C <= not (A and C); --F1 = combination logic
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end process;
13 end moore2_arch;
library IEEE; -- Moore2 machine example ,(complete program)
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use IEEE.std_logic_1164.all;
entity system is
port (
clock: in boolean;
A: in STD_LOGIC;
D : out STD_LOGIC );
-- since D is purely for output, no feedback read requirement, so it has the type
out
end system;
architecture moore2_arch of system is
signal C: std_logic;
begin
D <= not C; -- F2 = combination logic
process
-- sequential logic
begin
wait until clock;
C <= not (A and C); --F1 = combination logic
end process;
end moore2_arch ;
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Moore machine using 2 processes:
It is more flexible and easier to design.
You can make it formal that F1 is a process and
F2 is another process
Moore machine
1 architecture moore2_arch of system is
2 signal C: bit; -- global, can be seen by different
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3 begin
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process (C) -- combinational logic
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begin
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D<= not C; -- F2 = combination logic
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end process;
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process
-- sequential logic
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begin
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wait until clock;
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C <= not (A and C); --F1 = combination logic
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end process;
13 end moore2_arch;
library IEEE; -- Moore2 example ,-- synthesized ok.
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use IEEE.std_logic_1164.all;
entity some_entity is
port (
clock: in Boolean;
A,reset: in bit;
D: out bit -- no need to use inout or buffer type, since there is no need to
read.
);
end some_entity;
architecture moore2_arch of some_entity is
signal B,C: bit;
begin
process (C) -- combinational logic
begin
D <= not C; -- F2 = combination logic
end process;
process
-- sequential logic
begin
wait until clock;
C <= not (A and C); --F1 = combination logic
end process;
end moore2_arch;
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 Finite State Machine Applications:
State machines are used in a number of system control applications. A sampling of a few
of the applications, and how state machines are applied, is described below.
As sequencers for digital signal processing (DSP) applications, state machines offer speed
and sufficient functionality without the overkill of complex microprocessors.
For simple algorithms, such as those involved in performing a Fast Fourier Transform (FFT), a
state machine can control the set of vectors that are multiplied and added in the process. For
complex DSP operations, a programmable DSP may be better. On the other hand,
the programmable DSP solution is not likely to be as fast as the dedicated hardware approach.
Consider the case of a video controller. It generates addresses
for scanning purposes, using counters with various sequences and lengths. Instead of
implementing these as actual counters, the sequences involved can be “unlocked” and
implemented, instead, as state machine transitions. There is an advantage beyond mere
economy of parts. A count can be set or initiated, then left to take care of itself, freeing the
microprocessor for other operations.
In peripheral control the simple state machine approach can be very efficient. Consider
the case of run-lengthlimited(RLL) code. Both encoding and decoding can be translated into
state machines, which examine the serial data stream as it is read, and generate the output
data.
Industrial control and robotics offer further areas where simple control functions are
required. Such tasks as mechanical positioning of a robot arm, simple decision making, and
calculation of a trigonometric function, usually does not require the high-power solution of
microprocessors with stacks and pointers. Rather, what is required is a device that is capable of
storing a limited number of states and allows simple branching upon conditions.
Thank you
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