A STUDY OF MICROBUMP METROLOGY AND DEFECTIVITY AT 20
MICRON PITCH AND BELOW FOR 3D TSV STACKING
Leander Haensel, Maarten Liebens, Tom Vandeweyer, Andy Miller, Eric Beyne
IMEC
Leuven, Belgium
Leander.Haensel@imec.be
Markus Wiesiollek, Heiko Eisenbach, Marc Filzen, Youxian Wen, Sumant Sood
KLA-Tencor
Milpitas, CA, USA
Prashant.Aji@kla-tencor.com
ABSTRACT
As 3D TSV technology and 3D stacking moves into preproduction phase, the characterization of many of the
different critical modules within the TSV middle
integration flows becomes more and more crucial.
Microbump dimensions are being scaled down to
microbump pitch of 20 micron where the microbumps are
10 micron in width and 8 micron in height. This is required
in order to achieve higher interconnect densities. For dieto-die and die-to-wafer stacking, the need for highly
accurate and repeatable measurement of microbumps at
both die-level and wafer-level is an absolute must for this
technology to become a viable industrial option. For
process development, maximum possible number of bumps
needs to be characterized while for process monitoring, a
meaningful subset of bumps per die and dies per wafer have
to be qualified.
In this paper we show the fundamental requirement for
defectivity (damaged or missing bumps) and metrology to
be done simultaneously for complete 3D microbump
characterization. Additionally we discuss the challenges of
measuring 3D microbumps in terms of CD (Critical
Dimension), bump height, die-level bump coplanarity,
bump shape and finally the repeatability of those
measurements. Microbumps have been measured both pre
and post bump reflow at a wafer- and die-level, with a
statistical evaluation of measurement accuracy and
repeatability. The data shown is primarily concerning 20
micron bump pitch with additional data showing early 10
micron bump pitch activity.
Finally we show the differences in requirements for short
loop measurement capability vs fully processed wafers,
discussing the challenges introduced by multiple metal
layer patterning on pattern recognition and feature
recognition. We also perform an early assessment of the
increase difficulty of moving from 20 micron bump pitch
to 10 micron bump pitch on full flow wafers, examining the
uncertainty in measurement alignment and accuracy caused
by the increased background imagery.
Key words: Microbump, Metrology, Defectivity,
Coplanarity, 3D Packaging
INTRODUCTION
Over the last years, 3D TSV technology and 3D stacking
have moved from pathfinding to demonstration phase and
are now transitioning into pre-production. An integral part
of that transition is microbump scaling, enabling the higher
interconnect density that is one of the defining features of
3D stacking. With the current microbump design rule being
20 micron pitch and the experimental one being 10 micron
pitch, microbump dimensions (height and CD) are
venturing into target ranges of below 10 micron [1]. In
order for these microbumps to be usable for stacking, their
individual height and CD as well as the die-level
coplanarity have to be measured with a high accuracy and
precision such that the desired P/T≤10% can be achieved.
Coplanarity is of special interest, as it is the measure of
height variation of microbumps within a certain region.
Figure 1 shows this variation can be significant enough to
have serious implications for succeeding process steps like
wafer-level underfill applications, die-to-die and die-towafer stacking.
Figure 1. Coplanarity variation at 10 micron pitch
As coplanarity can be calculated in a number of different
ways in the context of microbump characterization, within
the scope of this paper peak-to-peak coplanarity will be
used. It is defined as the difference between the heights of
the tallest and the shortest microbump within a die as
shown in figure 2.
Figure 2. Peak-to-peak coplanarity
In addition to the metrology of microbump dimensions, the
defectivity of the dies and microbumps needs to be
characterized as well. Damaged or missing microbumps
absolutely need to be detected, as they will have a
significant impact on height and coplanarity results as
shown in figure 3.
Figure 3. Effect of damaged (top) or missing microbumps
(bottom) on coplanarity
A failure to properly characterize the coplanarity of each
die and detect defects of interest such as damaged, missing
or mislocated bumps can lead to the wrongful classification
of the die as suitable for further processing. This may have
a number of yield-affecting consequences during stacking,
such as open and short circuits, die cracking and thermal
sinks. As the typical die stack in high volume
manufacturing will consist of 8, 16 or more dies, a single
falsely classified die will affect the entire product.
Consequently, the impact of type II errors (false negatives)
will increase exponentially with number of dies in the
stack.
While the significance of metrology and defectivity
characterization in the microbump and the impact on
stacking have been outlined, the required scope of this
characterization needs to be addressed. For process
development, it will be of interest to characterize every
bump in each die, every die on a wafer. The wafers used in
the work for this paper is based on approximately 3800
bumps per die and approximately 2300 dies per wafer. This
results in a total count of close to 9 million microbumps per
wafer. Assuming a relaxed target measurement time of 1
hour per wafer that may be acceptable for process
development, the number of microbumps measured per
second would be roughly 2400. While options to measure
and analyze features at this rate exist, the results of these
techniques will show too low of a precision. Techniques
that are capable of measuring heights and CDs of 10 micron
and below at higher precision typically require a
measurement time between 1 second and 1 minute per
feature. So in choosing the measurement technique, a
compromise between measurement speed, number of
microbumps sampled and achievable precision has to be
made. The current target for process development of
measuring every bump on a wafer is not achievable in a
practical manner. But for process monitoring, measuring a
significant subset of microbumps per die and dies per wafer
can be sufficient.
Because defectivity doesn’t face the same restriction
regarding throughput as metrology does, microbump
characterization can be designed as a hybrid approach of
metrology sampling and in addition inspecting the full
wafer including all microbumps. This allows to understand
the microbump height, CD and coplanarity on a die- and
wafer-level while also detecting the aforementioned critical
defects and correctly classifying dies as defective. Ideally
the defect inspection precedes the measurement so it can
inform which microbumps or dies to exclude based on
already detected defects.
METHODOLOGY
Equipment
All primary microbump characterization work described in
this paper was performed on a KLA-Tencor CIRCL-AP
cluster system, using the 8905i and the Micro300 modules.
The 8905i module was used for full wafer defect
inspection, using rule-based binning for defect
classification. The Micro300 module was used for high
magnification optical review of the detected defects as well
as height and CD metrology of microbumps.
Supporting data was created using an Applied Materials
SEMVision (tilted SEM images), KLA-Tencor HRP340
(height reference values) or KLA-Tencor eCD2 (CD
reference values).
Samples
The samples used for the work described in this paper are
all based on IMEC’s PTCO mask set (Packaging Test Chip,
generation O). The microbump mask of this set is designed
with a maximum packing density of 50% at a pitch of 20
micron. Variations in the patterning and plating processes
allow the creation of smaller microbumps for the
experimental 10um pitch design rule. An overview of the
microbump’s target dimensions can be found in Table 1.
For both these variants, samples pre reflow as well as post
reflow were used, the significance of which will be
elaborated on in the process development section below. In
addition, short loop and full loop samples of the 10 micron
pitch variant were characterized, as the differences in
appearance and topography pose additional challenges as
will be discussed later in this paper.
Table 1. Overview of microbump’s target dimensions
Pitch size
Diameter
Height
Coplanarity
(micron)
(micron)
(micron)
(micron)
20
8.5
9.5
1.0
10
3.8
5.0
1.0
Process
Before recipe development began, reference values for
height and CD were collected by the aforementioned tools.
While understanding the offset and correlation between
these techniques and the KLA-Tencor CIRCL-AP was of
interest as a prerequisite for future process development
and monitoring, no special attention will be given to the
accuracy within the scope of this paper.
Development of characterization recipes began with 20
micron pitch short loop wafers, which only had undergone
the microbump patterning, plating, resist strip and seed etch
steps. This allowed working with as little extraneous
sample properties as possible, as visualized in figure 4.
Figure 4. Optical microscope image of 10 micron pitch
microbumps on short loop (left) vs. full loop (right) wafer
The reason for this approach lies in the inherent challenge
of measuring 3D features such as microbumps, especially
as they are further scaled from generation to generation. In
order to measure a microbump with repeatable results, it
has to be detected and the measurement subsystem needs
to align to it. Not only is that complicated by the extraneous
visual information of a full flow wafer, but by the
processing state of the microbump itself. Initial
microbumps followed the Cu only approach of copper
pillars, which lead to a very geometric pillar shape
including a smooth plateau top. Yet most current
microbump schemes have moved away from Cu only and
are now based on solder stacks such as Cu-Ni-Sn. The
consequence of such stacks is that the freshly plated stack
exhibits a very rough top (pre reflow) or a rounded, domeshaped top (post reflow). While a Cu only microbump will
present itself in an easily detectable geometric shape in an
optical top-down image, this is not the case for solder stack
microbumps as shown in figure 5.
Once the obstacle of properly detecting microbumps of any
process state has been overcome, the next challenge is
properly identify the center of each microbump, so that
height and CD measurement subsystems can properly align
and measure the microbump. Considering the
aforementioned topography of solder stack microbumps
and the fact that typical height measurement spots have an
diameter of roughly 10% of the diameter of a 20 micron
pitch microbump, it is easy to deduce that even a slight
positioning inaccuracy of a few micron will have a
significant impact on the measured microbump height as
shown in figure 6. Therefore, measuring every bump at the
same position, ideally the center, is important in achieving
a high precision on individual bumps and a pre-requisite for
high sensitivity with regards to coplanarity.
Figure 5. SEM (top row) and optical microscope images
(bottom row) of microbumps 20 micron pitch: Cu only
(left), solder stack pre reflow (middle) & solder stack post
reflow (right)
A considerable amount of the metrology recipe
development was spent in developing a best known method
(BKM) for discovering and addressing these challenges in
an iterative manner. Eventually, a solution involving
development and optimization of algorithms and detection
settings was found. Recipes to understand the effectiveness
of the solution and qualify the metrology capability could
be set up.
Figure 6. Solder stack microbumps 20 micron pitch with
indicated height measurement spot positioning
inaccuracies (red).
Following the metrology recipe set up, the defect
inspection recipe was created. Initial set up was done with
a focus on sensitivity to identify the defect types that could
potentially be detected and reported as defects of interest.
The goal was to have as wide a variety as possible and then
identify each type as either defect of interest or nuisance
defect. The latter were going to be suppressed and not
reported in the final defect inspection recipes, as they are
typically either non-critical or artifacts of the interplay
between sample and inspecting system. This selection
process was done based on tilted or TopSEM review and
discussions with the process engineers involved in the
microbump process module.
Following the finalization of characterization recipes for 20
micron pitch microbump short loop wafers, development
continued with 10 micron pitch microbump short loop
wafers. Due to the reduced dimensions, the challenges of
feature detection and alignment for metrology needed to be
addressed again. Further improvements in stage
positioning were key to enabling this.
Third and final stage of development was the
characterization of 10 micron pitch microbump full loop
wafers. This step introduced the extraneous visual
information caused by the presence of a full logic chip prior
to microbump formation. Understandably, the automatic
detection and measurement spot alignment shown in figure
7 was the major challenge to be addressed at this stage yet
again. This change in the optical image didn’t just
complicate the metrology, but also the defectivity set up, so
within the scope of work of this paper optimization of the
defect inspection on these samples was deferred.
Figure 7. Detection and measurement spot alignment (red)
on 10 micron pitch microbump (full loop).
Analysis
To qualify the metrology capabilities of final recipes for the
various sample types, a practical subset of microbumps
across the wafer was chosen. It consisted of 36 microbumps
per die and all dies along the horizontal and vertical
diameter of the wafer were chosen (approx. 52 dies per line
scan). In the interest of runtime, only 3 repeats of each
sample and recipe were run in order to determine the
precision of the height and coplanarity metrology and the
sensitivity to within wafer variation (see figure 8).
Figure 8. Sampling scheme for metrology qualification
As metrology of height and coplanarity was the main focus
of metrology recipe development for all 10 micron pitch
microbump samples, CD values were acquired but not
analyzed for these.
For defectivity recipes, recipes were also run 3 times, but
only a basic analysis based on the repeatability of defect
count per identified defect type was done. This ensured that
reported defects did in fact correlate to condition on the
wafer. With that certainty, randomly selected defects of the
various types were imaged using tilted SEM to identify
their defining characteristics and allow classification as
defect of interest or nuisance.
RESULTS
Height & coplanarity metrology
Analyzing the precision of height metrology yielded results
which were in line with some expectations, but provided
valuable insight on others (see Table 2).
As expected, precision was better on 20 micron pitch than
10 micron pitch samples, as the absolute system-induced
uncertainty will be the same regardless of sample and will
consequently have a greater impact on smaller target
dimensions. It was also expected that all other factors being
equal, short loop samples would yield slightly better results
than full loop samples. This can be explained using the
concept of most height metrology techniques. The height is
determined by measuring the reference z-level besides the
feature, the z-level on top of the feature and then
subtracting the former from the latter. On a short loop
wafer, there are only microbumps and flat, blanket wafer
surface in between them. The reference z-level won’t be
impacted at all. In contrast, on a full loop wafer ample
amount of topography is surrounding the microbump, be it
the pad it was built upon or any other kind of feature (refer
to figures 4 and 7). Depending on where the reference zlevel is acquired, small but significant differences will
impact the height measurement.
The unexpected outcome of the precision analysis was
precision pre reflow being significantly better than post
reflow on both 20 and 10 micron pitch samples.
Considering the previously explained differences in surface
condition (also see figure 6) and that feature alignment had
been improved to target the center of the bump, this was
quite surprising. Allowing for a certain minimal
positioning inaccuracy, aligning on the center of a
microbump post reflow will always measure it at or close
to the highest point of its surface, whereas measuring the
center of a microbump pre reflow may hit the highest point,
lowest point or anything in between. As of the time of
writing this paper, no comprehensive explanation has been
found.
Table 2. Height metrology precision of various
microbump sample types
Pitch size Pre/post
Full/short
Precision
(micron)
reflow
loop
(3σ in %)
20
Pre reflow
Short loop
2.9
20
Post reflow
Short loop
4.5
10
Post reflow
Short loop
6.0
10
Pre reflow
Full loop
5.4
10
Post reflow
Full loop
7.8
After assessing the precision of the height measurement at
bump-level, the repeatability of average height on die-level
(based on 36 microbumps per die) was analyzed, serving at
the same time as a gauge for sensitivity to within wafer
variation. The results can be seen in figure 9 through 13 and
generally show a very repeatable height measurement.
Regardless of sample, the within wafer variation is
captured, which means existing uncertainties are of a low
enough scale that sensitivity to wafer-level differences is
ensured. Yet, in line with previous observations on height
measurement precision, the post reflow samples are more
prone to variations from run to run, as seen in figures 10
and 13.
the resulting relative coplanarity plotted as shown in
figures 14 and 15.
Figure 9. Average microbump height repeatability;
sample: 20 micron pitch, pre reflow, short loop
Figure 14. Relative coplanarity of 20 micron pitch samples
(horizontal line scan only)
Figure 10. Average microbump height repeatability;
sample: 20 micron pitch, post reflow, short loop
Figure 15. Relative coplanarity of 10 micron pitch samples
(horizontal line scan only)
Figure 11. Average microbump height repeatability;
sample: 10 micron pitch, post reflow, short loop
Figure 12. Average microbump height repeatability;
sample: 10 micron pitch, pre reflow, full loop (due to
shortened sample availability only half the dies measured)
Figure 13. Average microbump height repeatability;
sample: 10 micron pitch, post reflow, full loop
Lastly of importance when qualifying height metrology is
coplanarity. As noted in the introduction, for the purpose of
this paper, peak-to-peak coplanarity is being evaluated. For
this, the range of the 36 measured bumps of each die is
calculated. The maximum range value of all 3 runs for each
die is chosen and normalized to that dies target value and
For 20 micron pitch samples, the resulting relative
coplanarity is in the realm of 10 to 20%. The coplanarity
pre reflow is on average higher than post reflow, which
given the surface conditions highlighted in figure 6 is to be
expected.
This difference can also be observed for 10 micron pitch
samples, where again the relative coplanarity values on the
sample pre reflow are on average 50-100% higher than
those of the samples post reflow. What’s more important to
note about the results on the 10 micron pitch samples
though are the values themselves. With the height target
value being cut roughly in half compared to 20 micron
pitch and the relative coplanarity almost doubling, the
logical conclusion is that the absolute coplanarity values
measured are more affected by whether or not the sample
was reflowed and whether it was a short loop or a full loop
than the target height respectively the pitch of the sample.
When looking at figures 14 and 15 it lastly has to be noted
that a few high values can be observed. Reviewing the
alignment images of the bumps in these dies showed that
the outliers were caused by an improper alignment of the zlevel measurement of either the reference or the feature.
While the root cause needs to be identified and addressed,
from a process monitoring perspective it is non-critical to
have a false high coplanarity value for a die. This would
result in this non-defective die to be classified as defective,
i.e. a false positive, which is preferable to a defective die
being classified as non-defective, i.e. false negative.
CD metrology
For CD metrology of 20 micron pitch microbumps, the
analysis of the 3 runs yielded an average precision of 3σ =
3%. The within wafer and within die variation was in line
with previously obtained reference metrology. As an
example see figure 9.
loop sample, pre reflow, exhibiting a special signature
around the outer edges of the wafer. Reviewing a select
number of defects via tilted SEM revealed these defects to
be predominantly particles. The sensitivity to this defect
type was verified on other samples types as well, albeit with
significantly lower defect levels.
Figure 16. CD average and range per die (line scan along
the horizontal diameter); sample: 20 micron pitch, post
reflow, short loop
Defectivity
An often used method in qualifying the sensitivity of defect
inspection techniques is the use of programmed defects [2].
These are deliberately created minute differences in feature
shape or position in one or more dies of a reticle, which
then transfer during wafer patterning. They can be detected
regardless of detection approach being used by the
inspection system, e.g. die-to-die or die-to-reference.
The PTCO microbump mask contained a set of
programmed defects. Specifically two different arrays of 6
bumps with slight shifts in position, which should repeat
every 4 dies in horizontal and every 2 dies in vertical
direction. These defects were the first focus when assessing
the defect inspection results. The difference image in figure
17 visualizes the mode of detection for these program
defects. All pixels in white represent parts of a feature
detected in the reference image which were not re-detected
in the sample image. Conversely, all black pixels belong to
a feature detected only in the sample image, but not in the
reference image. Grey pixels are representative of no
difference between reference and sample image, so either
pixels not belonging to a feature in either image or pixels
belonging to a feature in both images. So interpreting the
difference image, the top bump has a shift left, the right
bump a shift down compared to the reference. Also shown
in figure 17 is the defect map for these program defects,
which shows the expected periodicity in horizontal and
vertical direction.
Figure 18. Defect map & SEM image of sample surface
defect; sample: 20 micron pitch, pre reflow, short loop
The third and first microbump-related type of defect
studied was one occurring very frequently. Common
property of all microbumps classified as this type was a
bright reflex on top of the bump as shown in figure 19.
Upon SEM review, these microbumps exhibited surfaces
with large facets at a certain angle. As the illumination
incidence angles in the used defect inspection and review
subsystems are not perfectly normal to the stage and wafer
surface, these facets reflected a higher portion of the light
than the rest of the microbump and surroundings, causing
them to be detected as defects. As this type of defect is a
result of interplay between defect inspection subsystem and
inconsequential microbump properties, this defect type was
classified as nuisance and to be filtered out.
Figure 19. Optical microscope & SEM image of
microbump with bright reflex; sample: 20 micron pitch, pre
reflow, short loop
Figure 17. Difference image & defect map of programmed
defects; sample: 20 micron pitch, post reflow, short loop
Second category of defects to assess were surface defects,
which can range from particles over scratches to residues.
Figure 18 shows the defect map of a 20 micron pitch short
In contrast, the second type of microbump defect found
presented itself with dark reflexes, often also slightly
protruding from the circular shape. SEM review revealed
these microbumps to have one or more pits in the top layer
of the solder stack, an example of which can be seen in
figure 20. As these pits are effectively missing volume in
the solder stack, they would result in lower microbump
height after reflow process, which in turn could have a
negative impact on coplanarity of the die. Consequently,
this type of microbump was deemed a defect of interest.
used for this process characterization. They were
representative of microbump integration schemes at 20 and
10 micron pitch, extracted at two integral steps in the
microbump process flow, pre and post reflow, and both
short and full loop wafers were utilized.
Figure 20. Optical microscope & SEM image of
microbump with dark reflex; sample: 20 micron pitch, pre
reflow, short loop
The four types of defects discussed so far are not affected
by whether or not the sample was a short loop or full loop
wafer. As the potential sources for defects are considerably
higher on full flow wafer, these were studied next, using 10
micron pitch samples. Even with the increased amount of
visual information, surface defects like scratches or
particles could reliably be detected as shown in figure 21.
This paper further discussed the challenges of height and
CD metrology, particularly those related to quantity of data
to be acquired as well as desired precision and contrasted
them with the constraint of measurement time. This lead to
the proposal of a compromise in using a sampling scheme
focused on a practical subset of microbumps that would
allow die- and wafer-level characterization. Increasing
measurement speed per feature while retaining a high
precision on height and CD metrology will effectively
increase the number of microbumps that can be sampled
and therefore increase the confidence in the sampled subset
being representative of the actual die- and wafer-level
variation. One of the challenges in constituting a
meaningful subset is to define a population of microbumps
which is large enough to be statistically significant and to
select microbumps from areas in the die which will
represent height range and coplanarity of the full die.
Metrology precision in particular was shown to have
potential for further refinement. Primary goal for that is
improving the precision of coplanarity measurements, but
with further microbump scaling factors like feature
detection and alignment as well as measurement spot size
in relation to feature size will have an impact as well.
Figure 21. Surface defects (left: scratch, right: particle);
sample: 10 micron pitch, pre reflow, full loop
A new type of microbump-related defect that hadn’t been
encountered before on the short loop samples were
damaged microbumps, which presented themselves in
various forms. As can be seen in the pre reflow example
shown in figure 22, these microbumps can be misshapen
and forming bridges or blobs. The post reflow example
adds toppled over microbumps as well, which can have a
multitude of root causes. As any of these microbumps
result in the corresponding die being not suitable for further
processing, this type was also classified as a defect of
interest.
Figure 22. Microbump defects; sample: 10 micron pitch,
full loop (left: pre reflow, right: post reflow)
CONCLUSION
This paper discussed the fundamental requirement for
hybrid characterization of microbumps by combining both
defectivity and metrology data. A variety of samples was
Finally, a variety of detected defect types was investigated
and classified into nuisance and defects of interest.
Especially the microbump-specific defect types of missing
solder or damaged microbumps are critical to yield of 3D
stacking and can be detected with the developed recipes.
The technique used for defectivity was shown to be well
suited for 20 and 10 micron pitch. Accuracy and purity of
the identified defect types will have to be assessed and the
sensitivity especially to microbump-related defects will
require scrutiny as scaling continues.
ACKNOWLEDGEMENTS
The authors would like to thank John Slabbekoorn for
providing the large variety of microbump sample wafers to
allow a comprehensive study. Furthermore, we thank Inge
De Preter for the excellent SEM images. Lastly, we express
our gratitude towards Karen Stiers, whose previous work
on the aspects outlined in the introduction formed the basis
for this study.
REFERENCES
[1] Y. Ohara, A. Noriki, K. Sakuma, K-W. Lee, M.
Murugesan, J. Bea, F. Yamada, T. Fukushima, T. Tanaka
and M. Koyanagi (2009). “10μm Fine Pitch Cu/Sn MicroBumps for 3-D Super-Chip Stack“ from IEEE International
Conference on 3D System Integration, 2009.
[2] Suzuki K., Smith B. (2007). Microlithography: Science
and Technology, Second Edition. Boca Raton, FL: CRC
Press. p493-494.