Computational Methods in Nanoelectronics WS11/12
Project Report: IMOS-Based Inverter Simulation
Matthias Ritter 03290417, Sam Maurus 03614909
January 19, 2012
1
Introduction
As part of the course in Computational Methods in Nanoelectronics at the Technical University of
Munich (winter semester 2011/2012), students were tasked with using commercial software to
simulate the operating characteristics of a particular electron device – the IMOS. In addition to basic
device simulations, this project saw the simulation of a basic logic gate (an inverter) built from two
individual IMOS components.
This document reviews the foundational theory of an IMOS-based inverter and describes the approach
taken to perform the required simulations. Following this, the simulation results are presented and
discussed.
2
Theoretical Fundamentals
The following subsections discuss various physical fundamentals IMOS devices and then advance to
discussing the theory of an IMOS-based inverter
2.1 Impact Ionisation
Impact ionisation is the name given to the process in which a charge carrier (either an electron or a
hole) with enough kinetic energy promotes a valence-band electron to a conduction-band electron
through the donation of its own energy, thereby creating an electron-hole pair and leaving behind a
lattice ion [1]. This elementary act is pictured in Figure 1. Impact ionisation is thus the inverse of
Auger recombination, which is also a three-particle process in which an electron and a hole
recombine, thereby releasing energy that is transferred to a third charge carrier.
Figure 1: Elementary act of impact ionisation (reproduced from [2])
This act of ionisation is the basis of all ionisation, breakdown and avalanche effects [2]. The
minimum energy needed by a charge carrier such that it can cause an impact ionisation event is equal
to the ionisation threshold energy 𝐸𝑡ℎ . The threshold energy depends on the band structure of the
semiconductor, and the laws of energy and momentum conservation stipulate that the threshold
energy must be larger than the energy gap 𝐸𝑔 of the semiconductor.
The rates at which electrons and holes ionise is given by two constants, 𝛼 and 𝛽, which define the
reciprocal of the average distance (measured in the direction of the electric field) travelled by
electrons and holes respectively before creating an electron-hole pair by the impact ionisation process.
For example, a high value of 𝛼 corresponds to the case in which a free electron is likely to quickly
cause an impact ionisation event.
Avalanche multiplication occurs when electron-hole pairs are created by impact ionisation in a
fission-like manner. That is, avalanche occurs when the charge carriers resulting from an impact
ionisation event are themselves the catalyst for further impact ionisation events. Avalanche
multiplication is thus the cause for an exponentially increasing conduction-band charge density [3].
The realisation of this ‘running away’ process is termed avalanche breakdown.
If a high electric field is applied across a semiconductor, the temperature (i.e. kinetic energy) of the
charge carriers increases [4]. ‘Hot’ carriers that have an energy level greater than 𝐸𝑔 are able to
trigger impact ionisation events. The probability that a charge carrier is able to cause an act of impact
ionisation therefore increases vastly with an increase in the strength of the electric field in which it is
located [2]. By applying an electric field to a semiconductor, one can therefore control to a large
degree the level of impact ionisation that occurs within that semiconductor. This idea is exploited by
p-i-n structures like the IMOS devices which were simulated in this project.
2.2 Operational Theory: P-I-N Diodes
2.2.1 Construction, Material Selection and Doping Characteristics
A p-i-n diode is a p-n junction with an additional intrinsic layer sandwiched in the middle, as shown
in Figure 2. In practice, the idealised i region has a finite amount of n-type doping or p-type doping
[5].
Figure 2: Basic p-i-n structure
The P+ (p-type semiconductor) and N+ (n-type semiconductor) regions are obtained by doping the
semiconductor with acceptors and donors in the desired regions respectively [6]. Group-III elements
(e.g. boron) can be chosen as acceptors since they have three valence-shell electrons. After three of
the electrons form covalent bonds with a silicone atom, one additional hole remains which at room
temperature is free to act as a mobile positive charge carrier. The region thus contains an excess of
positive charge carriers.
Group-V elements (e.g. arsenic) can be chosen as donors since they have five valence-shell electrons.
After four of these electrons form covalent bonds with the silicone atoms, one additional electron
remains which at room temperature is free to act as a mobile negative charge carrier. The region thus
contains an excess of negative charge carriers.
For reasons discussed in section 2.2.2, the doping levels typically have values above 1018 cm−3.
2.2.2 Avalanche Breakdown in P-I-N Structures
In Figure 2 one can observe from left to right a basic p-i-n sandwich structure. If reverse bias is
applied to the p-i-n structure, most of the potential difference 𝑈 is supplied to the intrinsic region [7].
At lower reverse-bias voltages there exists only a small saturation current with negative charge
carriers moving towards the N+ region and positive charge carriers moving towards the P+ region
[8]. As the applied potential increases, more and more charges are accumulated at the junctions. If 𝑈
is high enough and the levels of n- and p-type doping are high enough (typically values above
1018 cm−3), the electric field established in the junction reaches values close to the breakdown field,
impact ionisation begins uniformly throughout this region and avalanche breakdown ensues [9].
Avalanche breakdown in a p-i-n structure such as that shown in Figure 2 can hence be achieved if the
reverse bias voltage and doping levels are high enough. As discussed in section 3, this project heeds
both of these requirements in order to simulate the avalanche breakdown effect in the IMOS structure.
2.3 Operational Theory: IMOS
2.3.1 Basic Concept
An impact-ionisation metal-oxide-semiconductor field-effect transistor (IMOS) builds upon the p-i-n
diode theory discussed in section 2.2. An IMOS is a hybrid between a transistor and a p-i-n diode in
that it adds a gate terminal to the intrinsic region which lies between the p-type region and the n-type
region. In basic operation, the p-i-n structure is biased close to breakdown using the source and drain
voltage and the gate terminal is then used to control the avalanche breakdown of the device, thus
switching it from the OFF state to the ON state and vice-versa [10].
2.3.2 Variants of the IMOS and their construction
There exist two main variants of the IMOS, namely the n-channel IMOS (hereafter referred to as
NMOS) and the p-channel IMOS (hereafter referred to as PMOS). In both of these variants, as with
any transistor, the resistance between two of its terminals is controlled by a third terminal [11].
The two variants are distinguished only through the positioning of the gate terminal in the device, as
shown in Figure 3.
Figure 3: Basic N-channel IMOS (left) and P-channel IMOS (right) structure. The difference between the devices lies
only in the positioning of the gate contact.
From Figure 3 it is observable that both the PMOS and NMOS share common structural
characteristics. The p-i-n sandwich structure is the same as for a p-i-n diode as discussed in section
2.3.2. The buried oxide functions as an insulator layer and the gate oxide is a dielectric layer that
separates the gate terminal from the conductive channel that connects the source and drain when the
transistor is turned on.
2.3.3 Device Operation
As introduced in section 2.3.1 and shown in Figure 3, an IMOS is essentially a gated reverse-biased
diode where the gate does not extend over the entire length of the channel. The gate underlap region
(i.e. the section of the intrinsic region not covered by the gate) is where impact ionisation occurs and
is the key to the operation of the device [12].
When a zero gate voltage 𝑉𝐺 = 0 is applied to an IMOS, the device is in the OFF state. In this state,
the reverse bias (chosen at design time) across the source and drain is not sufficient to cause impact
ionisation in the body of the device. In this state, the leakage current of the device is limited by the
reverse-leakage current of the p-i-n structure [10].
To consider what happens in order to bring the device into the ON state, we will first consider the
NMOS variant. In order to switch an NMOS to the ON state, 𝑉𝐺 is increased (i.e. moved from zero to
a positive voltage). This increased positive voltage causes negative charge carriers (electrons) to
accumulate under the gate where an inversion layer forms. As 𝑉𝐺 increases further, the fraction of the
drain-source voltage 𝑉𝐷𝑆 that falls over the gate underlap region increases, which in turn increases the
lateral electric fields in this region. Conceptually and effectively, the gate voltage pushes 𝑉𝐷𝑆 to the
edge of the gate. Once 𝑉𝐺 is high enough, the effective length of the intrinsic region is approximately
equal to the length of the gate underlap region and the electric field in this region is then large enough
to cause avalanche breakdown [12].
Bringing the PMOS variant to the ON state involves this same principle. The source and drain are
again set to a suitable reverse voltage, however 𝑉𝐺 is this time decreased (i.e. moved from zero to a
negative voltage), resulting in positive charge carriers accumulating under the gate. This has the same
effect: when the magnitude of the gate voltage is large enough the length of the intrinsic region is
effectively equal to the gate underlap region and avalanche breakdown occurs.
2.4 Operational Theory: Inverter
2.4.1 Basic Concept
The inverter (NOT circuit) performs a basic logic function called “inversion” or “complementation”.
This function changes one logic level to its opposite level. In terms of digital bits, it changes logic 1 to
logic 0 and vice versa [13]. In terms of input and output voltages, a ‘high’ input voltage results in a
‘low’ output voltage and vice versa.
2.4.2 Inverter Construction
An inverter can be constructed using one NMOS and one PMOS as shown in Figure 4.
Figure 4: Basic inverter schematic based on the NMOS/PMOS combination.
The input voltage 𝑉𝑖𝑛 serves as the gate voltage for both the NMOS and the PMOS. Adopting a
source/drain convention of the IMOS devices as shown in Figure 3, the ‘low’ reference voltage 𝑉𝑆𝑆 is
connected to the source of the NMOS, and the ‘high’ reference voltage 𝑉𝐷𝐷 is connected to the drain
of the PMOS. The drain of the NMOS and the source of the PMOS provide the output voltage 𝑉𝑜𝑢𝑡 .
2.4.3 Inverter Operation
A low input voltage 𝑉𝑖𝑛 causes breakdown in the PMOS device as described in section 2.3.3,
switching it to the ON state. The NMOS remains in the OFF state due to the low gate voltage. The
effective resistance of the PMOS device in the ON state is small, such that output voltage 𝑉𝑜𝑢𝑡 is then
approximately equal to the ‘high’ reference voltage 𝑉𝐷𝐷 .
In the reverse situation, a high input voltage 𝑉𝑖𝑛 causes breakdown in the NMOS device as described
in section 2.3.3, switching it to the ON state. The PMOS remains in the OFF state due to the high gate
voltage. The output voltage 𝑉𝑜𝑢𝑡 is then approximately equal to the ‘low’ reference voltage 𝑉𝑆𝑆 .
Thus, a low input voltage results in a high output voltage and vice versa. This is the fundamental
operational principle of the inverter. The ideal voltage transfer curve for an inverter is shown in
Figure 5.
Figure 5: Ideal voltage transfer curve for an inverter
3
Simulation
The following subsections discuss the various aspects of the simulations performed in this project.
3.1 Environment and Tools
The software package used for this project was Sentaurus Device. The package is developed by
Synopsis1. The various tools used from this package are listed in Table 1.
Table 1: Simulation tools used in this project
Tool Class
Device Modelling
Tool Name
Sentaurus Device Editor
(SDE)
Data Visualisation
Sentaurus Tecplot 360
Charting
Sentaurus Inspect
Usage Remarks
Used for geometrical device modelling and mesh
generation. Some manual editing of the modelling
files was performed to overcome some limitations
in the graphical user-interface.
Used to generate visualisations for results of
interest (e.g. electron/hole concentration)
superimposed onto the device structure.
Used for generating plots for simulation variables
of interest (e.g. current vs. voltage curves).
3.2 Modelling of Device Geometry and Materials
The individual IMOS devices (PMOS and NMOS) were modelled using Sentaurus Device Editor. A
formatted screenshot showing the geometry is given in Figure 6. From the scale the following
measurements are observable:


1
Gate width: 60nm
Source/drain width: 100nm each
http://www.synopsys.com/Tools/TCAD/DeviceSimulation/Pages/default.aspx

Buried Oxide: 500nm (w) x 300nm (h)
The gate oxide was modelled with a thickness of 3nm and a width of 300nm.
Figure 6: Geometry of the n-channel IMOS device. The p-channel variant is constructed by mirroring the gate about
the centre axis.
Figure 7 shows a Tecplot 360 screenshot of the doping profiles modelled in the device. The n- and ptype doping concentrations were set to a maximum of 1020 cm−3 in accordance with the requirements
discussed in section 2.2.2. Boron was used as the p-type dopant; arsenic as the n-type dopant. The two
doping profiles on each side of the device followed Gaussian distributions. The intrinsic region in the
middle was specified to have a finite p-type concentration of 1015 cm−3 in order to model it as
imperfect.
Figure 7: Doping profiles in the modelled device (here an NMOS). The gate oxide and electrodes have been edited
onto the image for reference.
3.3 Domain Discretisation (Meshing)
The next step in the simulation pipeline was to discretise the computational domain by using a mesh.
The mesh was generated using SDE’s inbuilt meshing function in combination with user-defined
mesh-refinement regions. Figure 8 gives an overview of the mesh, and the following points are
observable from the figure:


A coarse mesh is used in the bulk oxide region due to the fact that little or no movement of
charge carriers is expected within this region.
A fine mesh was employed in the area under the gate and the oxide interface, because it is this
region that sees the formation of the conduction channel and large changes in the density of
charge carriers.
Figure 8: IMOS mesh, showing the various refinement regions
3.4 Physics Modelling in Simulations
Various physics models were applied to the simulations. The models used are described in the
following subsections.
3.4.1 High-Field Saturation
If an electric field is applied across a semiconductor, a current is produced due to the flow of charge
carriers. Positive charge carriers (holes) flow in the direction of the field, and negative charge carriers
flow in the direction opposite to the field. In the case of small electric fields the drift velocity is
linearly proportional to the electric field [14]. When the electric field is sufficiently high, however, the
mobility decreases with the field linearly, and the drift velocity no longer increases but saturates [15].
The high-field saturation model in the simulation tool allows for this effect to be taken into
consideration and is enabled by including the keyword HighFieldSaturation in the relevant
Physics node of the command file.
3.4.2 Mobility degradation at interfaces
High transverse electric fields can be created by gate voltages in the channel region of a MOSFET.
For such fields, carriers can be drawn closer to the interface, thus increasing surface scattering (due to
acoustic surface phonons and surface roughness) and hence reducing mobility [16]. The mobility
degradation model in the simulation tool allows for this effect to be taken into consideration. The
Enormal keyword in the Mobility construct selects the calculation of the field perpendicular to
the semiconductor-insulator interface.
In addition, the PhuMob keyword was inserted into the Mobility construct in order to use the
Philips unified mobility model in the simulations. This model takes into account electron-hold
scattering, screening of ionised impurities by charge carriers, and clustering of impurities [17].
3.4.3 Band-to-band tunnelling: Schenk model
In cases involving high doping concentrations (as in this project) or in high normal electric fields,
phonon-assisted band-to-band tunnelling cannot be neglected. Enabling this model in the simulation
tool by using the keyword Band2Band and specifying Model=Schenk allows for these band-toband tunnelling effects to be considered.
3.4.4 Avalanche generation
As discussed in section 2.1, avalanche breakdown is caused by a chain reaction of impact ionisation
events. The ionisation coefficients 𝛼 and 𝛽 are dependent on the semiconductor material structure and
determine the rate at which electrons and holes ionise respectively. This important avalanche chargemultiplication effect can be modelled in the simulation tool by using the keywords Avalanche
(vanOverstraeten) in the relevant Physics construct of the command file.
3.4.5 Auger recombination
In the Auger process, the energy that is released during the recombination of an electron and hole is
not emitted with a photon, but rather transferred to a third particle. The third particle may be an
electron or a hole. This energy acquired by the (hot) third particle is eventually transferred from to the
lattice via phonon emission in a nonradiative manner. The simulation tool allows for the Auger
process rate to be defined using the Auger keyword in the relevant Physics section of the
command file.
3.5 Solver Description
The Sentaurus implementation of the coupled Poisson-electron-hole solver was used for the
simulations. This solver was specified using the statement Coupled { Poisson Electron
Hole } in the command file.
3.6 Gate-Independent Breakdown Simulations
Initial simulations were performed to elicit the reverse breakdown voltage of the p-i-n structure in the
modelled IMOS device. The corresponding theory is discussed in section 2.2. In accordance with the
theory, the gate voltage remained zero in these simulations. The following subsections describe the
results from the two corresponding simulations. A point of note is that one simulation was performed
on the NMOS structure and the other on the PMOS structure; this was purely arbitrarily and is also
irrelevant, because the gate voltage was fixed to zero in both simulations.
3.6.1 Source-Voltage-Induced Breakdown
In this simulation, the gate and drain voltages were fixed to zero. The source voltage was swept from
zero to -9 volts in order to capture the breakdown behaviour, as shown in Figure 9.
Figure 9: Setup for the source-voltage-induced breakdown simulation of the p-i-n structure in the IMOS
Figure 10 shows the resulting plot of source current against voltage. The vertical axis shows a
logarithmic scale.
Figure 10: Reverse-bias breakdown of the IMOS p-i-n structure by variation of the source voltage
This figure shows a typical breakdown curve for a p-i-n structure. Clearly observable is the
breakdown point, which occurs at around -8.5 volts. This breakdown voltage was noted for use in
later simulations.
3.6.2 Drain-Voltage-Induced Breakdown
In this simulation, the gate and source voltages were fixed to zero. The drain voltage was swept from
zero to 12 volts in order to capture the breakdown behaviour, as shown in Figure 11.
Figure 11: Setup for the drain-voltage-induced breakdown simulation of the p-i-n structure in the IMOS
Figure 12 shows the resulting plot of drain current against voltage. The vertical axis shows a
logarithmic scale.
Figure 12: Reverse-bias breakdown of the IMOS p-i-n structure by variation of the drain voltage
Once again the figure shows a typical breakdown curve for a p-i-n structure. Clearly observable is the
breakdown point, which occurs at around 11 volts. This breakdown voltage was noted for use in later
simulations.
3.7 Gate-Modulated Breakdown Simulations
Having completed the p-i-n structure simulations (see section 3.6), the next simulations that were
performed involved biasing the IMOS device close to breakdown and then varying the gate voltage to
induce breakdown. The relevant theory for this case is discussed in section 2.3. The following
subsections discuss the simulations for the two relevant cases: NMOS and PMOS.
3.7.1 Gate-Modulated PMOS Breakdown
In this simulation, the PMOS device was biased close to breakdown (considering the results from
section 3.6.2). The gate voltage 𝑉𝐺 was then altered from zero to -1 volts in a transient lasting 3ms.
The simulation setup is shown in Figure 13.
Figure 13: Setup for the gate-modulated breakdown simulation of the PMOS
Figure 14 shows the resulting plot of drain current against gate voltage. The vertical axis shows a
logarithmic scale.
Figure 14: Gate-induced breakdown of the PMOS
The breakdown can be observed from the figure occurring at around -0.55 volts.
3.7.2 Gate-Modulated NMOS Breakdown
In this simulation, the NMOS device was biased close to breakdown (considering the results from
section 3.6.1). The gate voltage 𝑉𝐺 was then altered from zero to +1 volts in a transient lasting 3ms.
The simulation setup is shown in Figure 15.
Figure 15: Setup for the gate-modulated breakdown simulation of the PMOS
Figure 16 shows the resulting plot of drain current against gate voltage. The vertical axis shows a
logarithmic scale.
Figure 16: Gate-induced breakdown of the NMOS
The breakdown can be observed from the figure occurring at around 0.6 volts.
3.7.3 Symmetry Observations
For a comparison of the breakdown curves for the PMOS and NMOS devices, the two respective
curves (Figure 14 and Figure 16) are placed side-by-side on an extended gate axis in Figure 17.
Figure 17: Combination of the gate-modulated PMOS and NMOS breakdown curves onto an extended gate-voltage
axis, showing the symmetry between the breakdown curves.
Figure 17 shows a desired property of the NMOS and PMOS devices – their breakdown curves are
approximately symmetric. This characteristic is supportive for the development of an IMOS-based
inverter, the simulation of which is discussed in section 3.8.
3.8 Inverter Simulation
3.8.1 System Modelling in the Sentaurus Command File
Arbitrary systems of components can be defined in detail in the Sentaurus command file. For the
inverter simulation it was necessary to define and specify the relationship (connections) for the PMOS
and NMOS components.
Both the PMOS and NMOS were defined in the command file using the Device construct. The
relevant device file, electrode definitions and physics models were defined for both the PMOS and
NMOS as follows:
Device PMOS {
File {...}
Electrode {...}
Physics {...}
}
Device NMOS {
File {...}
Electrode {...}
Physics {...}
}
The system of devices representing the inverter was defined in the command file using the System
construct. The construct allows for the connections between the individual devices to be specified as
follows (note that the connections are in line with the inverter schematic as discussed in section
2.4.2):
System{
NMOS a1 ( "source"=vss
PMOS a2 ( "source"=out
}
"drain"=out "gate"=in
"drain"=vdd "gate"=in
box=0 )
box=0 )
3.8.2 Simulation Results
The setup for the inverter simulation is shown in Figure 18. The connections of the system voltages to
the PMOS device and the NMOS device are described in section 3.8.1.
Figure 18: IMOS Inverter Simulation Setup
In order to bring the simulation to convergence, the final sweep of the gate voltage from -1 volt to 1
volt was done with the use of the Quasistationary method instead of the Transient method.
Figure 19 shows the output voltage transfer curve for the IMOS inverter, which can be compared with
the ideal voltage transfer curve as discussed in section 2.4.3. Although the switching point is not
centred at zero volts, the basic shape of the curve is clearly observable – a low input voltage produces
a high output voltage and vice versa.
Figure 19: Output voltage characteristic curve for the IMOS inverter
Figure 20 shows the output current (through the resistor 𝑅𝑜𝑢𝑡 ) for the IMOS inverter.
Figure 20: Output current (through a resistor of size 𝟏𝟎𝟏𝟐 𝛀) versus input voltage for the IMOS inverter
4
Suggestions for Further Work
A number of technical difficulties were experienced in this project relating to the convergence of the
inverter simulation. As such, limited time was available to ‘tune’ the inverter. One suggestion for
further work would be to experiment with the inverter parameters in order to further optimise the
inverter voltage transfer curve.
5
Conclusion
An IMOS is a hybrid between a p-i-n diode and a transistor. The two main variants of the IMOS – the
PMOS and the NMOS – were simulated in this project to obtain the basic characteristic breakdown
curves with and without gate modulation. Despite various differences in the operation of the devices it
was found that the gate-modulated breakdown curves are strikingly symmetric between the two
devices.
The symmetry of the NMOS and PMOS breakdown curves was an enabling factor for the simulation
of an inverter based on IMOS technology. Using one NMOS device and one PMOS device, a system
representing the inverter was defined in the simulation package. The subsequent simulation yielded an
input-output characteristic curve very similar to the expected results.
6
Acknowledgements
The authors wish to thank both Dipl.-Ing. Dan Popescu and Dipl.-Ing. Bogdan Popescu for their
invaluable assistance throughout the project, and in particular for their help in bringing the inverter
simulation to convergence.
7
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