US CMS HL-LHC PROPOSAL
Phase 2 Pixel/Strip Module Development
ABSTRACT
We propose to work on the development of the Pixel/Strip modules that will populate the
inner part of the upgrade CMS tracker in upgrade Phase II. These modules utilize
correlations between pairs of closely spaced silicon sensors to produce “stubs” with
nominal Pt above 2-3 GeV. These stubs reduce the data rate for transmission to offdetector track finding by a factor of ~twenty and enable the track-based triggering which
is a cornerstone of the Phase 2 upgrade. We also describe plans for expanded future
work on 3D active edge sensors.
1 R&D OVERVIEW
HL-LHC, with an average of 140 interactions per crossing, poses extraordinary
experimental challenges. Pileup backgrounds will degrade calorimeter resolutions,
triggers on missing Et will become more difficult, and raising thresholds on the
muon trigger beyond 30 GeV no longer provides significant trigger rate reduction.
Track information uniquely provides the ability to isolate the primary vertex and
reduce or eliminate backgrounds from pileup. Z vertex resolution is crucial. Full
track reconstruction with pixel hits can provide single vertex Z resolution. The PS
module is designed to provide intermediate, ~1 mm, Z tracking resolution for the
Level 1 trigger. This will reduce the combinatoric background by ~99% and also
provide a region of interest for the pixel readout which can be used for local readout
either at Level 1, if there is enough margin in the L1 latency, or to supplement Level
2.
Figure 1. CMS Phase 2 upgrade tracker design. PS modules are blue.
The planned CMS Phase 2 tracker is shown in figure 1. The PS modules occupy the
region between 20 and 60 cm in radius. Identical modules will be used in the barrel
and disk regions. A total of ~15,000 modules will be needed for the full tracker.
These devices will have unprecedented functionality and complexity. PS modules
are composed of long strip (LS) and short strip (SS) sensors. Hits from the long and
short strip sensors are clustered, compared, and combined in the MPA readout chip
to identify “stubs” where the offsets of the rphi hits in the two layers correspond to
transverse momenta greater than 2-3 GeV. Stubs are processed through an in-chip
pipeline to insure that on average a full event is read out every 25 ns. The z
resolution of the short strip sensor provides the information needed to resolve the
primary vertex when off-detector tracks are formed, but is not essential for stub
formation. The chip must also store and transmit full event data for those events
accepted by Level 1.
The PS module presents significant electronic, mechanical, and interconnect
challenges. The complexity of the chip itself is considerable. Connectivity
determines the module size. Two columns of eight reticule (typically at most 2x3
cm) sized MPA chips define the ~5cm x 10 cm module area. The two layers of
sensors must be separated by varying amounts, depending on the radius and
orientation of the module. The spacers between modules must be low mass and be
thermally conductive. A traditional pixel architecture that utilizes two columns of
readout chips with connections only at the outer edge cannot transmit hit
information between adjacent columns without the unacceptable complexity of
routing that information around the periphery of the module. This causes a dead
region for stubs where tracks pass between the low z and high z columns within a
module. This can be solved by adding connectivity, either with through-silicon vias,
an interposer, or utilizing a hybrid design using low profile wirebonds.
In previous years we had developed a complete track trigger conceptual design
within the context of the “Long Barrel” concept, with a “VICTR II” chip Verilog
design, system simulation, 3D chip prototypes, support structures based on carbon
fiber box beams, as well as a fairly complete conceptual design of off-detector
tracking. We hope to complete testing of these prototypes as we redirect our efforts
to the barrel-disk design. The barrel disk design poses different challenges and our
involvement will be more circumscribed. However we expect to build on our
previous work to develop interconnects, carbon foam technology, bump bonding
and assembly, and integrated circuit designs. In FY14 we plan to concentrate on PS
module and support design, prototyping, and testing. We will work closely with
CERN to develop these designs for the TDR. We also hope to explore TSV
technologies and possible interposer-based solutions. We plan to develop industrial
connections within the US for module assembly, TSV fabrication, and interposer
production. Finally, although not a component of this year’s proposal, we plan to
continue the development of 4-side-buttable “active tiles” which combine active
edge technology with 3D integration. These could lead to lower cost, fine pitch
pixelated sensor arrays that could be of great interest to both the HEP and BES
communities. Our plan is to pursue active edge tiles with generic R&D funds
through FY14, but expression of interest, eventual financial support, and
collaboration within the CMS context would be very valuable.
2 PARTICIPATING INSTITUTIONS AND PRINCIPAL INVESTIGATORS
 Cornell University – Jim Alexander, Anders Ryd, Julia Thom, Peter Wittich
 Brown University – Ulrich Heintz, Meena Naraian
 University of California, Davis – Max Chertok, Mani Tripathi
 University of California, Riverside – John Ellison, Gail Hanson
 University of California, Santa Barbara – Joe Incandela
 Fermilab – William Cooper, Stefan Gruenendahl, Marvin Johnson, Ron Lipton,
Lenny Spiegel
3 TECHNICAL DESCRIPTION AND DELIVERABLES OF THE PROPOSED
R&D
A. Full scale dummy module
The PS module is mechanically, thermally and electrically challenging. Signals from
the long strip sensor are amplified, discriminated, and then routed down to the MPA
short strip chips which provide the clustering, stub finding, and readout
functionality. DC-DC converters, concentrator chips and GBT transceivers are
located on the short edge of the modules. The most recent design simulations show
acceptable thermal performance with either carbon foam or carbon-fiber-aluminum
inter-sensor spacers. The short strip assembly consists of a 2x8 array of MPA chips
bump bonded to a sensor with 1.5 x 0.1 mm pitch.
We propose to build and test a full-scale dummy sensor/MPA assembly. This will be
done in close collaboration with the DESY and CERN module and electronics design
efforts. We will fabricate both dummy sensors and dummy MPA chips with the
correct bump bond pitch and chip spacing. These parts will also have serpentine
heating elements to simulate the power dissipation in the chips and sensors as well
Figure 2 PS module design (version 2.4)
shown on a carbon fiber-faced carbon foam
cooling tube support.
Figure 3 Dummy module sensor and chip layout
showing staggered bump bonds, serpentine heating
elements, and pads for daisy chain testing.
as daisy chains for interconnect testing and regions where alternate interconnect
ideas can be tested. These parts can be used as building blocks for thermal testing
and development of assembly techniques for the full module. We will then work
with industry to assemble prototype dummy sensor/MPA assemblies that will be
used for thermal and mechanical studies.
Deliverable – Dummy readout chips and bumped sensors
Deliverable – Assembled dummy PS module
Deliverable – Dummy module thermal, electrical, and mechanical tests
B. MaPSA-Lite Development
In parallel with the development of dummy module components the first step in the
development of integrated devices will be the development of a small demonstrator
Figure 4. MaPSA-Lite sensor (yellow) and ROIC (green)
module with 4 readout chips with 16 phi and 3 z channels each. The chip will be
designed at CERN in 65 nm with a full analog front end and simplified digital serial
readout. In parallel with our work on the dummy module we will explore fabrication
of the MaPSA-lite assembly with US companies as part of a feasibility study for full
module assembly. The MaPSA-lite can be tested with the CERN GLIB or more flexibly
with a National Instruments Flex-Rio system. If necessary we will develop circuit
boards to interface the MaPSA-lite with the National Instruments test systems
available at Fermilab, Brown, and Cornell.
Deliverable – MaPSA-lite PCB
Deliverable – MaPSA-lite assembly
Deliverable – MaPSA-lite tests
C. Mechanical and thermal testing
The PS module depends on novel, low mass high thermal conductivity materials for
acceptable thermal performance, especially after irradiation. Our previous design
was based on carbon foam and we have built and tested dummy modules with this
material. We have also procured and done some initial characterization of ALCF
material. We propose a program of test devices and measurements to understand
the thermal and mechanical properties of the carbon foam, how to incorporate
carbon foams into support structures, and optimal techniques to fabricate high
thermal conductivity interconnects.
It will be desirable to have uniform thin layers of epoxy applied to silicon and
carbon foam surfaces for the purpose of making stacks. The method needs to be
repeatable and have a good rate of production for large-scale module fabrication.
Earlier techniques, employed in HEP and elsewhere, have relied on shims to define
the thickness – epoxy is applied to surfaces and excess is removed using a razor
blade, or equivalent tool, that is wiped along the shims. We propose to use a robotic
dispenser made by EFD Nordson, which is in use at the Facility for Interconnect
Technologies at UC Davis. The dispenser uses a piezoelectric actuator to squeeze
controlled amounts of paste from a syringe – we have consistently deposited 130
um solder balls using this system. In this study, we propose to first deposit a matrix
of controlled amounts of epoxy and hardener on glass slides, observe the spread of
the mixture after applying pressure, and measure the resultant thickness of the
epoxy layer. The quantity deposited per squeeze and the pitch of the drops can be
varied until desired thickness of about 20-30 um is achieved. We will next apply the
technique to carbon foam attachments to silicon wafers, and perform mechanical
strength measurements.
Figure 5.Thermal conductivity test setup
Figure 6 UC Davis clean room
In order to fully implement the epoxy in the thermal modeling of the stacks, we need
to carefully measure the coefficient of thermal conductivity of a thin layer of epoxy
contacting to carbon foams and other materials. We are proposing to build a test
set-up that will be used for various samples, as well as for testing fully assembled
stacks. The set-up is based on earlier efforts of this nature, albeit with some
modifications that simplify the apparatus. Figure 5 shows the basic elements of the
test jig. The assembly is enclosed in a vacuum chamber to reduce heat loss due to
convection. The heat flow is measured above and below the sensor to ensure
thermal isolation. Temperatures are measured at 4 points each above and below
the sample to get enough data points to fit the thermal gradient and extract the
temperature drop across the sample. The coefficient of thermal conductivity can be
extracted knowing the heat flow and temperature drop across the sample. We will
design and build the system at UC Davis with help from our machine shop and
electronics shop. A readout system using LabView will be implemented to control
various sensors and record the measurements.
We plan to design, fabricate, and test carbon fiber-faced carbon foam rod support
structures with imbedded CO2 cooling pipes. These parts are in an early stage of
conceptual design and will require engineering design, short prototype fabrication,
and thermal and mechanical testing.
Deliverable: Thermal and mechanical tests of thin epoxy carbon foam layers
Deliverable: Design, fabrication, and testing of rod support structures
D. Interconnect R&D
Interposer
with analog
signals
Long Strip er
Long Strip er
Pixel er
~mm
Pixel er
Pixel er
Flex
~mm
interconnect
Carbon Foam
TSV
Long Strip er
~10 cm
Long strip signals pass through flex
Long strip are ½ module length
~10 cm
~10 cm
Figure 7. Possible interconnect topologies a) edge interconnect b) TSV-based c) Interposer-based
The PS module poses special interconnect challenges. Long strip information must
be conveyed to the pixel chip that forms the inter-tier coincidence. Information on
hits and clusters must be conveyed between chips in both r-phi and z to avoid holes
in stub acceptance. This is particularly challenging in the z direction, where
information is passed between columns. Figure 7a shows the “baseline”
configuration, where all information is passed along the edge of the module. There is
no provision for Z interconnect and all chip IO, strip input from the top tier, and
power connections are concentrated on a single edge. Inserting TSVs as in figure 7b
can solve the problem of z interconnect, distribute power and ground on the surface
of the chip and relieve some of the congestion at the edge. An interposer-based
design (figure 7c) provides Z interconnection, removal of congestion at the edge by
routing the digital signals to the center of the module, and the possibility of
integrating the functions of the long and short strip chips into one IC.
We propose to pursue both the TSV and interposer approaches. We had started
collaborating with CERN on their 3-T TSV development project last year. However
the company that originally quoted on the TSV work raised their price from $85k to
$150k, beyond our available funding. The current price for dedicated TSV insertion
at Tezzaron/Novati is also about $150k, and therefore is probably too expensive to
fund this year unless it is more clearly on the baseline development path. However
there is now a prospect of fabricating TSVs in a multiproject run. This would
considerably lower the cost and provide a clean development path for TSV–based
chips. We would pursue the TSV work this year only if there is an opportunity to
demonstrate the technology affordably.
ROIC
wirebonds
ROIC
Sensor
Figure 8a Low profile wirebonds
Figure 8b. Sketch of a wirebond-based column
interconnect
We have developed a conceptual design for an interposer-based module with
options for a silicon or glass/TSV-based device as well as a more standard PCB
interposer. Both of these designs are based on moving the p-phi connections
outboard and ganging the inner pixel to allow space for digital connections in the
center of the module. Space between chips in r-phi is generated by rerouting the
bond pads slightly inboard using 96 rather than 100 micron pitch. The PCB
approach has the disadvantage of larger via size (~80 microns), and larger feature
size than silicon or glass. The thicker dielectrics in PCB mean that controlled
impedance traces must be larger. Both effects make it more difficult to compress the
digital section to a small (~6 mm) area. PCBs also have significant thermal
expansion coefficient mismatch with silicon (10-20 vs 3 ppm/degree C) that can
result in unacceptable warping of the assembly. Either silicon or glass-based
interposers can solve these problems. Silicon interposers have a perfect CTE match,
can provide <10 micron routing, 10-50 micron vias with thin (micron-level)
dielectrics. Glass interposers have similar properties but with smaller dielectric
constant, simpler via etching but poorer thermal conductivity. We plan to
investigate glass or silicon interposer solutions as part of the dummy module work
only if costs for prototypes are affordable (less than $30,000). This appears likely.
We have recently had discussions with companies building glass interposers and
may be able to share an interposer development test run with a run for x-ray
imaging focal planes funded by BES/Argonne.
The Facility for Interconnect Technology at UC Davis maintains capabilities for flipchip bump-bonding using a variety of techniques, including gold-stud bonding,
indium-bump bonding, solder-ball reflow bonding, and anisotropic conductive film
attachments. We use the Northern California Nanotechnology Center on UC Davis
campus for mask making, photolithography and wet chemistry for wafer fabrication.
We will design and fabricate dummy sensors and dummy read-out chips, which will
be used to make mock-ups of the stacks. We will pattern traces on the dummy ROIC
to be used as heaters to mimic the power dissipation. The dummy sensors will also
have loop-back test structures to measure bump-bonding yield. As part of this
proposal, we will finish the work on bump-bonding of VICTR chips with pcb
interposers and sensors from BNL
We have also started to study a more conventional approach, where low profile
wirebonds nestle under the bump bonds and provide a signal path between the MPA
chip columns. In our initial attempt (figure 8a) the wirebond height was measured
to be between 50 and 93 microns. We then added a 50 micron spacer to the top chip
and glued a glass slide to the surface, compressing the bonds to 50 microns. There
was no apparent issue with bond breakage. This solution has its own issues. The
proximity of the digital signal-carrying bonds to the sensor surface means that the
sensor would have to be shielded, presumably by a cu-kapton ground plane glued to
the sensor surface. The bump bonds should have a standoff of 100-150 microns.
Such a design would have to be tested in a bump bonded assembly. Digital pickup
would also have to be measured. The dummy module discussed in part A has
provisions for such testing. Although not as elegant as the interposer and TSV
solutions this (or a variant) may be the most inexpensive means of achieving intercolumn communication.
Deliverable – Interposer or TSV demonstration devices
Deliverable – Wirebond interconnect studies
E. Testing of the VICTR 3D chip
The VICTR chip was designed and fabricated as a demonstration of the use of 3-D
integrated circuit technology for the CMS track trigger. Through-silicon-vias
provide the ability for the circuitry to connect both to the top and bottom directly
and locally, enabling local formation of stubs with no need for edge communication.
The 3D interconnect therefore allows for fabrication of larger sized (10x10 cm)
modules with direct vertical analog connections between the long and short strip
tiers. This technology is no longer the baseline, due to the slow development of the
technology and the issue of yield of the 25 chips that would have to be bonded to the
sensor surface. This is addressed in active edge R&D.
Figure 9. Test results for VICTR showing noise and
threshold distributions
Figure 10. Sensor mounted on top of
VICR through a PC board interposer
VICTR consists of two tiers of 0.13 micron CMOS circuitry. The two tiers are bonded
face-to-face on 4 micron pitch with Direct Oxide Bonding (DBI) technology. We
have completed the first phase of VICTR testing without sensor and have confirmed
the basic functionality of the chip including communication between tiers. We are in
the process of testing the long strip tier of the VICTR with a sensor bump bonded to
the top through an interposer.
In the final phase of this work the VICTR chips (and its cousins VIPIC and VIP) are
being DBI bonded to a sensor wafer provided by Brookhaven. This work is in
progress at Ziptronix and delivery is scheduled for January. We propose to test this
assembly on the bench, and if the bench tests are successful add the interposer/top
sensor assembly to complete the 5 layer 3-D stack. The resulting assemblies would
then be tested in the Fermilab test beam.
Deliverable – Test of the short strip – VICTR stack
Deliverable – Assembly and test of the 5-layer stack
Deliverable – Beam tests of stacked sensors and ROICs
F. ASIC Design
We are in discussion with the CERN microelectronics group on the development of a
radiation hard static RAM in 65 nm. This “IP” would be utilized both in the MPA chip
and a future pixel readout chip. The development of this custom SRAM requires
custom design tools and memory “compilers”. The Fermilab ASIC group is
investigating the resources necessary to develop the capability for such custom
memory compilation. Assuming the answer is positive we have included funding for
initial design and verification work for the SRAMs. Submission and irradiation of
test structures would occur in future years.
Deliverable: Design and simulation of a 65 nm radiation hard SRAM IP
G. Active edge/3D development
The most serious problem with our initial large module 3D design was the yield
associated with placing ~25 chips on a large sensor wafer. A compelling solution to
that problem is to combine 3D electronics, which offers the ability to provide
connections to both sides of an IC, with active edge sensor processing, which allows
silicon sensors to be butted on all 4 sides with minimal loss of active area. This
would provide individual sensor/ROIC “tiles” which can be thoroughly tested and
then bump bonded into large area assemblies. In addition, this allows connections to
be made on a wafer scale, simplifying the process, allowing very fine pitch and
lowering the cost.
Deposit amorphous silicon
Die 1
CMOS Wafer
Die 2
CMOS Wafer
Sensor wafer
readout
IC and pads
200 micron
Buried
oxide
sensor
trenches
3D bond
CMOS Wafer
Sensor wafer
Etch
Handle wafer
Figure 11. Structure of the 3D/active edge
SOI stack
Thin, Expose top contacts, singulate
CMOS Wafer
Test, bump into assembly
PCB
Figure 12. Simplified 3D/active edge process based on
plasma dicing and amorphous silicon contacts.
Our current project, funded by generic R&D, is intended to demonstrate a combined
3D/active edge process using SOI active edge wafers from VTT and dummy ROIC
wafers from Cornell. The process used for the current demonstration has
disadvantages in the complexity of the SOI sensor wafer and the complex
singluation process. Since that project was initiated we have developed a simplified
scheme (figure 12) for producing these tiles where the active edge is produced by
plasma dicing (a standard industry process) and the backside contact to the diced
edges and the back side wafer contact is supplied by a doped amorphous silicon
layer. This also allows for straightforward fabrication of thinned, radiation hard
sensors on 8” silicon. We will test this process on spare test structures this year, and
if successful, expect to make a proposal for application of this process in the Phase 2
pixels or silicon-based calorimetry.
4 RELATION TO EXISTING EFFORTS
CMS has several alternate version of the “baseline” PS module. All of them will
require the type of bump-bonded structure we will provide in Task A. This work is
strongly coupled to both the module mechanical development development effort
and to the electronics assembly effort at CERN. Task B represents the US
contribution to the smaller scale 65 nm chip and sensor “MaPSA-lite” demonstration
project. This work is considered a first step in the development of an integrated
track trigger module. The MaPSA-lite will test the 65 nm front end chip and also
allow some testing of the integrated system. If properly designed it should also
allow us to test some schemes for inter-column communication.
Task C is focused on mechanical and thermal tests needed to validate the PS module
design. In particular high thermal conductivity carbon foam is an appealing
material for providing the spacer between sensors and is the baseline for the rod
support structure. Optimal thermal contact glues and the thermal resistance of the
glue interface cannot be calculated from first principles. A thermal test setup is
necessary to understand these basic parameters. This work will lead directly into
system cooling tests which utilized the CO2 test system which was built for CMS
pixels at Fermilab.
Some advanced form of interconnect is necessary for communication between
columns in the PS module (Task D). Here we can build on our extensive experience
with 3D (through-silicon-via) technologies and excellent industry contacts based on
our previous work on 3D circuits. We have discussed the “via-last” TSV
implementation with RTI, Tezzaron, and Allvia and believe that we can develop
prototypes quickly if funding is available. Our initial work on low profile
wirebonding is based on discussions with Sandro Marchioro at CERN. The
interposer design, although not the current baseline, has significant advantages and
has some interest within CMS. The Fermilab IC group is currently working with the
detector group at the Argonne Advanced Photon Source to develop a large-area
interposer-based sensor array for x-ray imaging. Costs can probably be shared with
this effort. A silicon or glass interposer is similarly a natural candidate to host sets
of associative memory chips for off-detector track finding.
Task E completes the existing effort on the VICTR chip and 3D design of the track
trigger module.
Task G is an outgrowth of our combined 3D work and large area module studies.
Initial studies are being performed in collaboration with SLAC, Brown and UIC. If
successful, the concept can be applied to large area pixelated arrays for the CMS
(and ATLAS) forward tracker extension, a possible silicon-based forward
calorimeter, x-ray imaging applications, and space science.
2
6
2
8
6
4
4
6
52
1/15/14
2/12/14
1/29/14
2/12/14
4/9/14
5/21/14
5/21/14
5/21/14
9/24/14
1/29/14
3/26/14
2/12/14
4/9/14
5/21/14
6/18/14
6/18/14
7/2/14
9/23/15
MaPSA-Lite
MaPSA design available
Design MaPSA test board
Fabricate MaPSA test boards
Assemble MaPSA-Lite
Test MaPSA-Lite
MPA component tests
3
4
6
12
50
2/15/14
3/8/14
4/5/14
5/17/14
3/1/15
3/8/14
4/5/14
5/17/14
8/9/14
2/14/16
Mechanical R&D
Thermal and mechanical tests of thin epoxy layers
Design, fabrication, and testing of rod support structures
Continue and refine rod support structure
12
40
40
1/15/14
1/15/14
10/22/14
4/9/14
10/22/14
7/29/15
Interconnect R&D
Design demonstration interposer/TSV
Fabricate demonstration interposer/TSV
Test demonstration interposer/TSV
Demonstrate alternate interconnect tech
8
12
24
16
1/6/14
3/3/14
5/26/14
2/1/14
3/3/14
5/26/14
11/10/14
5/24/14
11/10/14
5/24/14
12
2/1/14
4/26/14
2/1/14
4/26/14
6
4
12
18
4/26/14
6/7/14
7/5/14
9/27/14
6/7/14
7/5/14
9/27/14
1/31/15
ASIC Design
Design radiation hard SRAM IP
Fabricate rad hard SRAM
Test Rad hard SRAM
20
16
22
5/1/14
9/18/14
1/8/15
9/18/14
1/8/15
6/11/15
Active Edge/3D development
Receive 3D bonded wafers
Singlulate active die
Probe tests
Fabricate test modules
Bench test modules
Beam test modules
Test DRIE with test structures
Test backside processing with test structures
8
4
8
8
12
20
30
VICTR Chip Tests
Receive Oxide bonded chips/sensors
Test oxide bonded VICTR
If initial tests are promising:
Bump VICTR/SS to LS + Interposer*
Test 5-layer stack*
Beam test preparation*
Beam tests*
UCSB and UC Riverside participation to be determined.
4/9/14
X
X
X
X
X
X
X
UC Riverside
Receive funding
Full dummy module
Design dummy readout chips
Fabricate dummy readout chips
Design dummy sensors
Fabricate dummy sensors
Assemble dummy PSA module
Electrical tests of dummy module
mechanical tests of dummy module
Thermal tests of dummy module
Full module fabrication and testing
UCSB
End
Fermilab
Start
UC Davis
Milestone
Date
1/15/14
Duration
Cornell
Task
Brown
5 SCHEDULE AND MILESTONES
X
X
X
X
X
7/2/14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2/15/14
4/5/14
X
8/9/14
X
4/9/14
10/22/14
7/29/15
X
X
X
X
X
X
X
X
X
X
7/5/14
X
9/18/14
1/8/15
6/11/15
X
X
X
X
X
X
X
X
X
X
X
X
3/1/14
3/1/14
4/26/14
5/17/14
7/12/14
9/6/14
1/1/14
1/1/14
4/26/14
5/24/14
7/12/14
9/6/14
11/29/14
5/21/14
7/30/14
X
X
X
X
X
X
X
X
X
X
X
6 FACILITIES, EQUIPMENT, AND OTHER RESOURCES
Fermilab
 ASIC group Six member group with extensive resources and experience in IC
design. Unique experience in 3D integrated circuits.
 Flex Rio test stands Flexible FPGA based IC bench test system
 Silicon Detector facility - Large clean rooms with extensive infrastructure with
CMM machines, probe stations, wirebonding machines and test equipment
 Test Beam - The MTest primary beamline consists of a beam of high energy
protons (120 GeV) at moderate intensities ( 1-300 kHz). This beam can also be
targeted to create secondary, or even tertiary particle beams of energies down to
below 1 GeV, consisting of pions, muons, and/or electrons. This facility will be
used to test detector assemblies
 Carbon fiber fabrication facility
 CO2 cooling test facility in SiDet
 Thermal conductivity test facility in SiDet
Brown University
We have a wide range of equipment available for the work at Brown University.
We have two Rucker&Kolls semi-automatic probe stations, several oscilloscopes,
including a high-end model, programmable signal sources and voltage sources, an
LCR meter, Labview software and desktop computers needed to control the
equipment. National Instruments Flex RIO system.
UC Davis
 An electronics lab containing all the necessary test equipment for electronics
development, including modern oscilloscopes, a spectrum analyzer, a digital
analysis system and other characterization modules. The group also maintains
licenses for various design software packages for pc board layout, circuit
simulation, programmable logic etc. There is a 100 sq ft shielded room (Faraday
cage) for testing sensitive circuits.
 An Indium deposition system for forming indium bump bonds. This equipment is
housed in its own dedicated lab in the physics department.
 The Northern California Nanotechnology Center on UC Davis campus has a
10,000 square feet class 100 micro-fabrication facility that is available for use to
the faculty at a nominal fee. This facility has photolithography equipment
including a mask maker and a mask aligner, several stations for wet chemistry and
equipment for e- beam evaporation and sputtering.
 A bump-bonding lab (see picture below) consists of a class 1,000 clean room
equipped with several pieces of specialized equipment (acquired in 2010): 1) a
Signatone probe station, 2) a West Bond ball bonder, 3) a Fine Tech aligner
bonder, 4) EFD robotic dispenser and 5) a MannCorp programmable reflow oven.
We are in the process of acquiring a new aligner-bonder with the help of ARRA
funds. Research Devices flip-chip aligner/bonder and a probe station in a separate
class 10,000 clean room.
 Support using highly subsidized electronics and machine shops Mechanical
design
Cornell University

Nanofabrication Facility - The Cornell NanoScale Science & Technology Facility
(CNF) is a national user facility that supports a broad range of nanoscale science
and technology projects by providing state-of-the-art resources coupled with
expert staff support.
Simulation/Software including experience with Silvaco 3D TCAD simulation
Sensor and readout assembly & testing
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UCSB
 Machine Shop
 Clean rooms and infrastructure
 FPFA and ASIC design engineering
UC Riverside
 Machine Shop
 Clean room, probe station, semiconductor test equipment in Physics building
 UCR Center for Nanoscale Science and Engineering Nanofabrication Facility
available to faculty for hourly fee
7 BUDGET AND BUDGET JUSTIFICATION FOR FY14
An additional spreadsheet is included which breaks down cost by task and funding
source.
8 PRELIMINARY BUDGET AND BUDGET JUSTIFICATION FOR FY15
Describe activities foreseen to achieve the deliverables and provide a preliminary budget.