Performance advancement of High

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Performance advancement of High-K dielectric MOSFET
Neha Thapa1
M.E. Student
NITTTR, Chandigarh
er.thapaneha91@gmail.com
Lalit Maurya2
Er. Rajesh Mehra3
M.E. Student
NITTTR, Chandigarh
lalitmaurya47@gmail.com
Abstract--High dielectric gate oxide is a
strong alternative for replacing the
conventional oxynitride dielectrics in
scaled MOSFETs for both high
performance and low power applications.
The objective of this paper is to analyse
the performance of MOSFET with high
dielectric gate oxide. In this paper we
have shown a comparative study and
analysis of n channel MOSFET designed
with HFO2 in the place of silicon oxide.
Here we have been discussed the effect of
HfO2 gate oxide on drain current,
threshold voltage and substrate bias effect
for MOSFET. Design, Simulation and
analysis have been done with the help of
cogenda Visual TCAD.
Keywords High-k dielectric, N-MOSFET,
HfO2, Visual TCAD
INTRODUCTION
SiO2 has been used as an efficient gate
dielectricsince the advent of MOS devices
over 40 years ago. unlike competing
materials, silicon has dominated the industry
because it has an easily processable oxide
(i.e., it can be grown and etched). Various
Associate Prof. ECE
NITTTR, Chandigarh
rajeshmehra@yahoo.com
thicknesses of SiO2 may be required,
depending on the particular process. Thin
oxides are required for transistor gates and
thicker oxides might be required for higher
voltage devices. The oxide structure is
called the gate stack. This term comes up
because current processes not often use a
pure SiO2 gate oxide, but prefer to produce a
stack that consists of a few atomic layers,
each 3–4 Å thick, of SiO2 for reliability,
overlaid with a few layers of an oxynitrided
oxide (one with nitrogen added). The
presence of the nitrogen increases the
dielectric constant, which decreases the
effective oxide thickness (EOT); this means
that for a given oxide thickness, it performs
like a thinner oxide. Silicon dioxide has
traditionally been used as the gate insulator. The
gate oxide serves as insulator between the gate
and channel, which should be made as thin as
possible to increase the conductivity of the
channel and performance of the transistor when
transistor is on and to reduce subthreshold
leakage when the transistor is off.[1]
For increased speed at constant power
density the requirement has led to shrinking
of MOSFET dimensions and according to
scaling rules, the oxide thickness is also
reduced similarly. With scaling reaching
sub-100nm technology nodes,as scaling of
SiO2 below 3 nm causes serious problem
regarding tunneling current and oxide
breakdown so the introduction of novel
materials
became
certain.
Although
optimization using nitride/oxynitride gate
stacks were under pursue to lower the
leakage current but still a need for better
high-k materials to solve the issues such as
negative bias temperature instability and
mobility lowering [2,3].
threshold voltage. The threshold voltage can
be expressed as
The continually shrinking gate-oxide
thickness results in direct tunnelling[4] and
excessive leakage currents in Si-based MOS
devices. HfO2 is one of the material of high-
..(2)
k dielectric family can resolved this
problem.Hafnium Dioxide has relatively large
energy band gap and a good thermal stability as
compared to Si [5-7].HfO2 or Hafnia is the
inorganic colourless solid and stable compounds
of hafnium and also an intermediate which
provides Hf metal. It has relatively large energy
band-gap and a good thermal stability as
compared to Si. It is an electrical insulator with
a band-gap of 5.8eV [8-10]. HfO2 is inert and
respond with strong acids and strong bases and
dissolves slowly in HF acid to give
fluorohafnate anions. The use of HfO2 results in
many advantages over SiO2 [11].
In many digital circuit applicationsthe
source potential of an nMOS transistor can
be larger than the substrate potential, which
results in a positive source-to-substrate
voltage VSB>0.When a voltage VSB is
applied between the source and body, it
increases the amount of charge required to
invert the channel, hence, it increases the
..(1)
where Vt0 is the threshold voltage when
source is at the body potential, ϕs is
surface potential at threshold and γis
body effect coefficient, typically in
range 0.4 to 1 V1/2 which depends on
doping level in channel NA.
the
the
the
the
the
The surface potential and body effect coefficient
expressed as [12]
..(3)
For SiO2, εox = 3.9εo and for HfO2, εox= 25εo.
DESIGN AND SIMULATION :
The general processes to design 180nm
MOSFET involving simulation of fabrication
process, structure and mesh and electrical
testing. the first step for designing the MOSFET
is to draw the ‘device drawing’ using Visual
TCAD , further meshing is done. Meshing size
is tabulated below for different region :
Figure 1 : Mesh size for different Region
The doping profiles used in the the designed
MOSFET is listed as bellow :
Figure 2 : Doping Profiles
The designed structure of MOSFET and the
material used in structure are shown in figure 5
and 6
Figure 4 : Structure which show material used
RESULT AND ANALYSIS:
The effect oxide thickness variation in designed
MOSFET with acceptable level on the drain
current with the variation in gate voltage and
drain voltage is shown in figure 6 and 7
Table 1: Drain current with fix gate voltage
Drain
voltage
Figure 3 : Design Structure of n type MOSFET
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Drain
current for
SiO2
-1.92E-16
0.0003137
0.00054992
0.00068657
0.00073882
0.00075449
0.00076305
0.00076988
0.00077586
0.00078129
0.00078627
Drain
Current for
HFO2
-1.12E-16
0.00094338
0.00181288
0.00258343
0.00322934
0.00372686
0.00406017
0.00423508
0.00429992
0.00432411
0.00433851
5.00E-03
4.00E-03
4.50E-03
3.50E-03
4.00E-03
3.00E-03
3.50E-03
2.50E-03
3.00E-03
2.00E-03
2.50E-03
1.50E-03
2.00E-03
1.00E-03
1.50E-03
5.00E-04
1.00E-03
0.00E+00
5.00E-04
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0.00E+00
-5.00E-04
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain Curent for HfO2
Drain Current for SiO2
Drain current for SiO2
Drain Current for HFO2
Figure 6: Drain characteristics curve
Figure 5: Drain characteristics curve
Table 2: Drain Current with fix drain voltage
Gate
Voltage
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Drain
Current for
HfO2
1.15E-06
8.39E-05
0.0003434
0.00070981
0.0011393
0.00160781
0.0020941
0.00256675
0.00299931
0.00338502
0.00372686
Drain
Current for
SiO2
7.28E-12
2.19E-09
6.18E-07
2.19E-05
8.49E-05
0.00017288
0.0002753
0.00038702
0.00050522
0.00062813
0.00075449
Table 1 represent simulated spreadsheet for
drain characteristics of MOSFET in which drain
voltage varies from 0 to 2 volt with voltage
sweep 0.2 volt. Table 2 represent simulated
spreadsheet for transfer characteristics of
MOSFET in which gate voltage varies from 0 to
2 volt with voltage sweep 0.2 volt.
From the drain characteristics figure 6 we
analyze that drain current increases with
decrease in thickness of gate oxide and vice
versa.We find that the mobility of carriers in
HfO2 is more as compared to SiO2. Drain
current is directly proportional to the mobility
and oxide thickness per unit. These values are
larger in HfO2 as compared to large SiO2. Hence
the simulation result give large amount of
current achieved by using HfO2 for the same
applied voltage and aspect ratio. Further, from
the transfer characteristics figure 7 we analyse
that threshold voltage decrease with decrease in
oxide thickness. As we know that the value of
gate to source voltage required to cause surface
inversion is called the threshold voltage. Lower
value of threshold voltage is advantageous in
high speed applications.
Table 3: Drain current with substrate bias effect for
SiO2 type MOSFET
Dratn
current at
Vsb = 0v
Gate
Voltage
Drain
Current at
Vsb = 0.5v
Drain
Current at
Vsb = 1v
0
9.96E-12
2.54E-15
2.55E-15
0.2
3.12E-09
2.55E-15
2.54E-15
0.4
8.66E-07
1.00E-14
2.52E-15
0.6
2.59E-05
3.06E-12
2.54E-15
0.8
9.40E-05
1.31E-09
2.57E-15
1
0.00018644
4.96E-07
7.01E-15
1.2
0.00029275
2.23E-05
2.30E-12
1.4
0.00040807
8.94E-05
1.16E-09
1.6
0.00052974
0.00018178
4.94E-07
1.8
0.00065616
0.00028828
2.29E-05
2
0.00078627
0.00040376
9.09E-05
Figure 7: Transfer characteristics curve show substrate bias
effect in SiO2 type MOSFET
Table 4: Drain current with substrate bias effect for
HfO2 type MOSFET
Drain
current at
Vsb = 1v
Gate
Voltage
Drain
current at
Vsb = 0.5v
Drain
current at
Vsb = 0v
0
2.65E-15
9.09E-15
1.29E-06
0.2
2.70E-15
9.76E-12
8.93E-05
0.4
2.73E-15
1.51E-08
0.00035784
0.6
1.13E-13
1.25E-05
0.00073304
0.8
1.80E-10
0.00017746
0.00117143
1
2.88E-07
0.00049576
0.00165142
1.2
5.49E-05
0.00089931
0.00216024
1.4
0.00029311
0.0013556
0.00268982
1.6
0.00065055
0.00184711
0.00323439
1.8
0.00107615
0.00236316
0.00378918
2
0.00154358
0.0028958
0.00435006
Figure 8: Transfer characteristics curve show substrate bias
effect in HfO2 type MOSFET
The drain current curve with respect to the gate
voltage show the substrate bias effect. This
effect occurs when a voltage Vsb exists between
the source and bulk terminal of a MOSFET.
Figure 7 show that substrate bias voltage
increases the threshold voltage of the device.
Since we require low value, the simulated result
shown in table 4 and figure 8 give that Hafnium
(HfO2) is preferred for reducing the substrate
bias effect.
CONCLUSION :
The effect high-k dielectric Hafnium on the
characteristic curve of drain-source current verse
gate voltage/ drain voltage in designed
MOSFETs has been studied. By use of HfO2 in
place of SiO2without altering other parameters
the drain current value is noted. From the above
simulation we can conclude that replacing the
silicon dioxide gate dielectric with a high-κ
material allows increased gate capacitance
without the associated leakage effects.It is
concluded that HfO2 give large amount of drain
current and it is preferred for reducing the
substrate bias effect. Further we say that high-k
metal gate technology to be a strong alternative
for future nano scale MOS devices.
REFERENCES :
[1] Neil H. E. Weste, David Money Harris, "CMOS VLSI
Design ", fourth edition, Addison-Wesley, 2011.
[2] Sugiyama,Y., Pidin, S., Morisaki, Y. (2003).
Approaches to using Al2O3 and HfO2 as gate dielectrics
for CMOSFETs. Fujitsu Sci. Tech. J. 39, 94-105.
[3] Guha, S., Narayanan, V. (2009). High-κ/Metal Gate
Science and Technology. Annu. Rev. Mater. Res., 39, 181–
202.
[4] Razavy, Mohsen (2003). Quantum Theory of
Tunneling. World Scientific. ISBN 981-238-019-1.
[5]. H-H. Hsu, Y. Chang, J. Lee, IEEE Electr. Device L.
28, 964 (2007).
[6]. R.G. Southwick, J. Reed, C. Buu, R. Butler, G.
Bersuker, B.K. Knowlton, IEEE T. Device Mat. Re. 10,
201 (2010).
[7] J. C. Lee, “Single-layer thin HfO2 gate dielectric with
n+ polysilicon,” Proc. of IEEE Symposium on VLSI
Technology, NJ, June 2000, pp. 44-45.
[8] H. S. Baik and S. J. Pennycook, “Interface structure and
nonstoichiometry in HfO2 dielectrics,” IEEE Applied
Physics Letter, vol. 85, 2009, pp. 672- 674.
[9] A. P. Huang, Z. C. Yang, and Paul K. Chu, “Hafnium
based Highk gate dielectrics,” Proc. of Advances in Solid
State Circuits Technologies, April 2010, pp. 333-350.
[10] ‘A Product catalogue,’ READE Advances Materials,
England, 2005.
[11] M. Fadel and O. Azim, “A study of some optical
properties of hafnium dioxide thin films and their
applications,” J. of Applied Physics Materials Science and
Processing, vol. 66, no. 3, pp. 335- 343, 1997.
[12] Sung-Mo Kang, Yusuf Leblebici," CMOS Digital
Integrated Circuits", Third Edition, McGraw-Hill.
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