Adrian Ionescu
Nanolab, EPFL Switzerland
1

Prove that energy efficient
nanolectronics is a must for
the future…

… and NEMS is a potential
key enabling low power
technology.
2
Source: Heike Riel, IBM.
3
Power Density (W/cm2)
Power crisis in nanoelectronics
• Leakage power dominates in advanced technology nodes.
• VT scaling saturated by 60mV/dec limit, voltage scaling slowed.
1E+03
Active Power Density
1E+02
1E+01
1E+00
1E-01
1E-02
1E-03
1E-04
Passive Power Density
1E-05
0.01
0.1
Gate Length (μm)
Source: B. Meyerson (IBM)
Semico Conf., January 2004
1
4
20
-4
10
-7
Energy [Joule]
10

14
10
11
10
-10
10
8
-13
10
-16
10
10
5
10
-19
energy / logic operation
inverter only
incl. on-chip comm.
What matters:




17
10
Energy [kT]
p.
to t
in
n
po eve
g
in SE
at
lo
AP
/f
N
gy
SY
er
en IBM
/
gy
er
en
-1
10
Today
10

energy / computed bit
scaling
systemability
system level metrics prevail over
device level
Integrated approach for
energy/bit at system level:





Switch
Memory
Interconnects
Architecture
Embedded Software
2
10
10
3kT ln(2)
-1
10
1940
1960
1980
2000
2020
Year
5
VG
@ VD=Vdd
S avg  V T  V Goff  / log( I T / I off ) V
dd
/ log( I on / I off )
(mV/decade)
6

A fundamental issue?
S 
V g
 (log I d )

V g

S
  S  log I D 
  
m
m less than 1
active gate devices:
 NEM relay or NEMFET
 negative capacitance
 (1 
Cs
C ins
)
kT
ln 10
q
n
n less than (kT/q)ln10
# injection in the channel
 Tunnel FETs
 Impact Ionization MOS
7
 Nano-Electro-Mechanical (NEM)
Devices
 NEM switch
 NEM memory
 NEM resonators
8
 as a multi-state logic, with the logic
states dictated by a spatial configuration
of movable objects
 as vibrational modes of mechanical
elements, based upon waves.
 as a sensed or transduced signal
operation.
9
Source: G. Li et al, Urbana-Champaign.
10
Ideal
switch
Drain curret
• Advantages:
- zero Ioff (zero static power).
- abrupt transition between off
and on states.
• (Unwanted?) feature of NEM
switch:
- hysteresis due to different
values of pull-in, Vpi (off-on
transition) and pull-out, Vpo
(off-on transition) voltages.
MOS
switch
D
NEM G
switch
60mV/dec
Vpo
S
Vpi
Gate voltage
Pull-in voltage: V pi 
8 k eff g eff
27  0 A
11
• For low cost & high
performance, post-CMOS
integration is desirable.
• Thermal process budget is
constrained for MEMS
fabrication: surface
micromachining is low T
foundry CMOS
MEMS
Si Substrate
Source: T.J. King.
12
3-terminal relay:
Stanford
4-terminal relay:
UC Berkeley
2-terminal relay:
EPFL
OFF state
thin
oxide
Movable electrode
air-gap
source
gate
drain
insulator
Metal
air-gap
Si n+
insulator
substrate
substrate
ON state
anchor
air-gap
source
gate
insulator
drain
anchor
substrate
13
Gate
oxide
Nice but large
(10’s micrometer) size!
Scalable?
A
Body
Drain
27μm
0.3
2μm
CHANNEL
30μm
16μm
0.2
Drain current, IDS [mA]
19μm
5μm
12μm
GATE
GATE
3μm
1μm
5μm
ANCHOR
SOURCE
(b) AA’ cross-section: OFF-state
Gate
Source
IDS
Body
Channel
-1
1V
VG>VPI
0.1
0
0.5
-0.1
-0.3
VS=VB=0
VPI=6V
-0.4
(a)
1
Drain voltage, VDS [V]
10-4
1.00E-04
VD
100mV
VD=10mV
1V
100mV
VD=10mV
VB
VG
GND
10-6
1.00E-06
VS
p-relay
10-8
1.00E-08
VD
1.5
VG=5V
(<VPI)
-0.2
n-relay
10-2
BODY
BODY
-0.5
(c) AA’ cross-section: ON-state
1.00E-02
0
-1.5
Source
Insulator
Substrate
A’
Drain current, IDS [A]
15μm
DRAIN
VG=
1.1·VPI
1.2·VPI
1.4·VPI
1.6·VPI
1.8·VPI
2·VPI
Body
Drain
(a) Relay schematic
0.4
Gate
VDD
10-10
1.00E-10
10
VG
VB
-12
1.00E-12
VS=0
VDD=8V
VS
10-14
1.00E-14
-6
-4
(b)
-2
0
2
4
6
8
10
Gate to body voltage, VGB [V]
Source: V. Pott, T.J. King, UC Berkeley.
14
Nice,
small size!
Ioff excellent
But voltage
large: > 10V
Scalable?
W. W. Jang et al, Appl. Phys. Lett., 92(10), 103110, 2008.
15

CMOS to real logic mappping
Relay technology
F. Chen et al, ICCAD 2008.
16
Energy / useful bit = 10 pJ @ 2m ~1000 less than SoA
transmit energy + transmitted energy + receive energy
= signal processing +
front-end
PHY, MAC, NETW
= signal processing +
front-end +
sleep (“scan”) mode17
B. Halg, "On a micro-electro-mechanical nonvolatile memory
cell", IEEE Transactions on Electron Devices, Vol. 37, Iss. 10, 1990.
• thin micromachined
bridge elastically deformed:
two stable mechanical
states : “0” and “1”
• MOS process: Si02 layer bridge
covered by a 2nm thin Cr
• state of the bridge changed
using electrostatic forces
• read out by sensing the
capacitance
• Size: ~hundreds mm2
• Actuation voltage: > 40V
18
Y. Tsuchiya, K. Takai, N. Momo, T. Nagami, H. Mizuta, S. Oda,
"Nanoelectromechanical nonvolatile memory device incorporating
nanocrystalline Si dots", Journal of Applied Physics, 100, 2006.
19
W.Y. Choi; H. Kam; D. Lee, J. Lai, T.-J. King Liu, "Compact Nano-ElectroMechanical Non-Volatile Memory (NEMory) for 3D Integration", Technical
Digest of IEEE International Electron Devices Meeting, IEDM 2007.
R e a d w o rd lin e (R W L )
tgap2
tbeam
tgap1
A ir g a p 2
B it lin e (B L )
A ir g a p 1
O N O s ta c k
W rite w o rd lin e (W W L )
In s u la to r
• Nano-Electro-Mechanical NV memory
–
–
–
–
RWL as a top electrode
BL as a movable mechanical beam: information stored as BL position
ONO stack for charge storage
WWL as a lower electrode
20
F re s h n itrid e
C h a rg e -tra p p e d n itrid e
t g a p 1 “F re s h ” = n o c h a rg e tra p p e d in n itrid e
tg ap1
“1 ”
S h ift b y
V o ffs e t
V p u ll-in ’=
V p u ll-in - V o ffs e t
V re le a s e ’=
V re le a s e - V o ffs e t
“0 ”
V re le a s e
V p u ll-in
V B L -W W L
(= V B L - V W W L )
V re le a s e ’
V p u ll-in ’
V B L -W W L
(= V B L - V W W L )
• NEMory cell operation is based on the hysteretic behavior
of a mechanical gap-closing actuator.
• Charge in the ONO layer is used to shift the hysteresis curves
by Voffset, to achieve bistability at 0 V (VBL-WWL  VBL - VWWL),
thus enabling non-volatile storage.
21
J.W. Han, Jae-Hyuk Ahn, Min-Wu Kim, Jun-Bo Yoon, and Yang-Kyu Choi,
"Monolithic Integration of NEMS-CMOS with a Fin Flip-flop Actuated Channel
Transistor (FinFACT)", IEDM 2009.
Principle: laterally movable (suspended) silicon FIN, bistable & sensed by transistor
current flow.
22
- Depending on design
(width) can be used both as
NV (ROM) or SRAM.
- Trade-off between the
endurance and retention.
23
J.E. Jang et al, "Nanoscale memory cell based on a nanoelectromechanical
switched capacitor", Nature Nanotechnology, Vol. 3, Jan. 2008, pp. 26-30.
NEM switched capacitor structure based on vertically aligned MW CNTs
- Capacit. of CNT NEM DRAM cell
(diameter=60 nm; length=1.6 mm;
SiNx,=40 nm): value of 0.59 fF with
available potential of 2.4 mV for bit line
sensing in a conventional DRAM design.
-15 fF and 60–80 mV (Gbit DRAM)
possible by the integration of high-k
(not shown)
- voltages > 14V
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• comparable cell area
• scalable/comparable operation voltages
• lowest program/erase energy: sub-10-16 J/bit.
90nm Technologies:
NEMory
NOR Flash Phase-Change Memory
Ionic Memory
mechanical gap- charge on
reversible
Ion transport and
closing actuator floating gate material phase change redox reaction
Cell area
6~12 F2
10 F2
4.8 F2
5~10 F2
Program/erase time
0.9 ns / 0.3 ns
1 ms / 10 ms
50 ns / 120 ns
< 20 ns
Read time
>1.5 ns
10 ns
60 ns
<10 ns
Program/erase voltage
1.5 V
12 V
3V
< 0.5 V
Read voltage
3V
2V
3V
< 0.2 V
Program/erase energy 3  10-17 J/bit
10-14 J/bit
5  10-12 J/bit
10-15 J/bit
Storage mechanism
25
• Probably the most promising family of RF M/NEMS.
• Embedding full equivalent circuit functions (RLC) with very
high-Q and voltage tuning (possible replacement of quartz).
• Applications: oscillators, mixing, filtering, sensing.
Passive MEMS resonator
Adrian Ionescu, GRC 2012
Resonant body transistor
26 26
Fully-depleted RB-FET:
0.5 µm x 0.25 µm x 10 µm
Nanowire RB-FET:
40 nm x 40 nm x 2 um
NW-FET body


Frequency, mass, Q
mass & force detection
nm SOI-CMOS technology
integration density, complexity
400 nm
27

Tunable operation point:
 Trade-off: gain versus power.
 Experiment: resonance from strong to weak inversion.
 nW static power consumption in weak-inversion (PDC < PAC ).
S. T. Bartsch, A.M. Ionescu, IEDM 2010.
28
• Double-gate (in-plane) VB-FET resonator: transistor
detection improves output signal by more than
+30dB.
Transistor
Capacitive
D. Grogg et al, IEDM 2008.
29
•
•
•
•
Transistor-based homodyne / heterodyne mixing.
Mixing coupled to mechanical motion.
Signal-to-background improvement.
Applications: VHF mixer-filter, closed-loop configurations.
Imix ~ gm
S.T.Bartsch et al, ACS Nano 2011.
Cc-Beam: 0.15 x 0.2 x 3 µm3
f0=78 MHz, Q=1100
30


Highly sensitive integrated sensor arrays (~10-100 attogram)
Ultra miniaturized single-device radios (RF front ends)
31
Device concept:
• SW CNT instead of Si
• fres ~100MHz-1GHz
• strong piezores. Effect 2xf
• DG, 100nm airgap
• By resist-assisted DEP
(>107 CNTs/cm2)
Adrian Ionescu
Ionescu,
AdrianA.M.
Ionescu,
GRC 2012IEDM 2011
32 32
32 32
Source: Ji Cao, EPFL.
33


Energy efficient devices: a must for the future!
Challenges:
NEMS
Relays
• scaling of:
 gaps & size
 operation voltage
• reliability of contacts & packaging
• dedicated IC design
Resonators
• analog/RF & sensing
34
NEM memory:
 exploit the. electromechanical hysteresis of movable
structures by a gap closing Storage layer: specific
purpose for shifting the hysteresis (NEMory, Oda’s
memory, SG-FET)!
 excellent co-integration with silicon CMOS. Low
temperature processing, BEOL (3D-) integration possible,
low cost.
 Low voltage operation possible, limits ~1V
 Program/erase & read times: <10ns
 energy efficiency: less than 10-16 J/bit in NEMory & SBM.
 Trade-off between endurance & retention in FIN-FACT.
 Robust in high temperature and radiation environments.
 CNT-based memory: immature
 Promising for embedded memory applications
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