E Anantha Tirzha 1 , B V Pavan Kumar 2 , Naga Raju Ravada 3
Department of Electronics and Communication Engineering, Sasi Institute of Technology and Engineering, Tadepalligudem, India
1 anantha.tirzah@gmail.com
ABSTRACT
This paper discusses the efficient usage of the
Advance Encryption Standard (AES) that will be used to implement high secured and low power
Crypto design by using clock gating technique. blocks of 128 bits. In addition, the AES algorithm is an iterative algorithm. Iteration can be called as a round and the total number of iterations/round Nr, is 10, 12 or 14 when the key length is 128, 192 or
Clock gating technique is simple and effective method to reduce power dissipation.
KEYWORDS: Cryptography, clock gating, AES,
DES, TDES.
I INTRODUCTION
Most of the user now a day’s using wireless communication for fast sending and receiving the mails in less time and in less cost. When this way of communication is going on, the unauthorized people hack the information within that frequency.
Users has led to an improving security and protecting user provided data/transmitted data to the hackers. Two types of cryptographic systems are mainly used for security purpose, one is asymmetric key crypto system and another one is symmetric key crypto system. In asymmetric key crypto system uses different keys for encryption and decryption. In symmetric key system uses same key for both encryption and decryption. DES,
TDES and AES are the symmetric crypto systems,
Data encryption standard (DES) was FIPS approved cryptographic algorithm. FIPS publication gives mathematical calculations for
DES. The main drawback of DES algorithm is its key length is small [1][2].
Triple Data Encryption Standard (TDES) is another mode of DES algorithm. It uses three 64bit keys. The main drawback of TDES is three times slower than DES [2][3].
In 2001 National institute of standard and technology (NIST) selected the Rijndael algorithm as The Advance Encryption Standard (AES) to replace previous algorithm like DES [4][5].
Clock gating is a popular technique used in many circuits for control power dissipation by clock net.
In synchronous digital circuits the clock net is responsible for significant part of power dissipation
[6][7].
By using clock gating technique in ring counter with SR flip-flop this project to reduce the power.
The rest of the paper is organized as follows.
Section II describes AES algorithm, section III describes Key Generation module, section IV describes clock gating, section V describes results and finally we conclude the paper in section VI.
II AES ALGORITHM
The AES algorithm is a symmetric block cipher.
AES algorithm allows for the use of cipher keys that are 128,192 and 256 bits long to protect data
256 bits respectively. The 128 bit plain text is organized by 4x4 matrixes of 16 bytes called a state. After first XOR operation between k and plain text, the algorithm consists in several rounds.
Every round except last round performs four operations. In the last round does not execute the
Mix Columns transformation. Figure1 is the basic iterative implementation of AES algorithm [8].
It is mainly composed of key generation module and round module. In this iterative implementation, plain text and secret key given to
Addround key operation that is nothing but Xor operation and the output of Addround key is given to next transformations. Control block gives the round key that is 10, 12 or 14 to key generation block. The result of the each iteration of round module is stored into the register R1. After 10 iterations of round module, the controller set the encryption signal that loads the cipher text into the output register R2 [9].
For decryption, inverse operation of last round of encryption process is performed. Last round of decryption contains Inv Addroundkey, Inv Sub
Bytes and Inv Shift Rows. The explanations of four operations of encryption/decryption are AddRound key, Sub Byte, Shift Rows and Mix Column as follows.
A. AddRound Key/ Inv AddRound key
AddRound key is simple bitwise Xor operation.
After every round output of the MixColumn operation is added with Addround key [10][11].

B. SubByte /Inv Sub Byte Transformations
In this transformation stage, every byte of the output stage of AddRound key replaced by byte stored in look up table is called S-Box or
Substitution Box. The S-box is 16x16 matrixes of bytes consist of all possible combination of 8-bit sequence.
In the inverse Sub Byte step, each byte in the matrix is updated with the inverse 8-bit S-box
[10][11].
C. Shift Row /Inv Shift Row Transformation
Shift Row transformation is simple permutation.
First row of the state is kept as same while second, third and fourth rows are cyclically left shifted by one byte, two bytes and three bytes.
Inverse Shift Row transformation is same but second, third and fourth rows are shifted cyclically to the right. Shift Row transformation is shown in
Figure2 [11].
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Figure2.ShiftRow Transformation
D. Mix Column Transformation
In this transformation, each column of the state matrix is treated as a four-term polynomial. Each column is multiplied by a matrix with a fixed polynomial of GF (2 8 ). Inverse Mixed Column stage use different multiplier constants [10][11].
Mixed Column Transformation is shown in figure3.
XOR operations with RCON. Figure4 is the key generation block [12][13].
Figure4. Key Generation Block Diagram
RCON is a register constant value. It is a user provided constant value. Rotation word is nothing but the word is cyclically shifted to the right.
In Sub word operation, the operation of the Rot word is substituted in the Key memory.
In Key XOR operation RCON value is ‘XORed’ with the first word and the result of the XOR operation is again XOR with the second word. The same procedure is performed with W[i-N k
].Each round of the final value is stored in array register to start the next iteration of the key generation[12][13].
IV CLOCK GATING TECHNIQUES
Clock gating is a technique where the clock signal prevented from reaching the various modules of the processor. The absence of the clock signal prevents any register and or flip-flop from changing their value. Gating is achieved by ANDing the clock signal with a clock gated control signal, whenever any module of circuit that needs to be gated clock activated otherwise low [14].
Figure3.MixColumnTransformation
III Key Generation Module
In the AES algorithm, key generation module is used for generating round keys for every round and it generates a total of N k
(N r
+1) words. Once the key expansion is done the key data is used for encryption and decryption. First of all divided the initial key into N k
words (key0, key1 ...keyN
k-1
) which are used as initial keys.
In each round of key expansion it has to pass through key rotation word, key sub word and key
Figure5. Block of memory organization
The memory organization of AES algorithm this block diagram as shown in figure5. In this 32-bit ring counter is connected to the memory block.
In this research work, ring counter with SR flipflop. The clock gating technique is used in ring counter with SR flip flop as shown in figure 6.

“faaee88aa01a8158” is given as input and secret key, when control ‘1’then encryption process is occurred and generated round keys and then get the output as 6e1f686ea93a31fca86f3d072215b7b1 as shown in Figure7.
Figure6. Clock gating ring counter with SR
Flip-flop
In the memory block, we have to choose only one location at a time. But in that time the whole memory is activated, so that power consumption is more.
In Figure6, the ring counter with SR flip-flop is divided into two blocks and each block is connected to the clock gating technique. Initial value is clock signal and every time only one block is activated and another one is low [14][15].
In memory only one location/row is activated and consume power at that location the remaining locations are inactive, so we reduce the power consumption [14][15]. Power results are shown in section 5.
V RESULTS
As long as the clock is in active state, control signal decides the operation of Advanced Encryption
Stand, either encryption with secret key or decryption with secret key.
The active high control signal exhorts the AES as encryption. The 128 bit hexadecimal data to be encrypted and another 128 bit encrypting pseudo random code will be applied to it.
AES will perform Add round key, Shift Row,
Mixed column and Sub byte operations. The input to the above operations will be provided by the Key generation block of AES which intern consists
Rotation word, Sub Word and Exclusive OR operation with Register constant value.
Active low control signal exhorts the AES as decryption, which will get encrypted data as input.
This decrypted performs reverse operations to the predefined four transformations.
Figure8: Simulation of AES Decryption
The encryption output is given to the input decryption it will get the output faaee88aa01a8158 when control ‘0’ as shown in Figure8. Finally encryption input obtained at decryption output with less power consumption.
Proposed crypto core design using clock gating optimized 57.1% of power utilization.
SYNTHESIS RESULT
PARAMETER EXISTING PROPOSED
Power 385mW 165mW
VI CONCLUSION
In this work, we have presented a hardware implementation of AES algorithm of
Encryption/decryption, Key generation Block and clock gating technique. In this process, the power consumed by the proposed system is less compare to the existing system by using clock gating technique.
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Figure7: Simulation of AES Encryption

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