EE 435: Project One
Kyle Lichtenberg
EE 435: Project One
Two Stage Fully Differential Operational
Amplifier Design
Iowa State University
Kyle Lichtenberg
Iowa State University: Department of Electrical Engineering
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EE 435: Project One
Kyle Lichtenberg
Introduction
In this project, a two stage fully differential amplifier had to be designed and tested using
knowledge and experience from the class. The design had to meet strict specifications,
and required: Vdd=5 V, Vss=0 V, CL=5 pF, and a generated Iref=10 μA. Also, a common
mode feedback circuit had to be included to ensure circuit stability. In all, this project can
be thought of as being built in four stages. These stages are: the first amplifier stage, the
second amplifier stage, the common mode feedback circuit, and the current generator.
Experiment
It was decided early on that the first stage would be a common source amplifier, and the
second stage a cascade configuration containing four pairs of transistors. The sizing of
these transistors were centered on the given specifications, mainly the slew rate and gain
bandwidth product. Since CL and Cc were known, the transconductance and current could
easily be found, and with these values, the sizing could then be determined. The
following schematic shows the common source first stage:
Iowa State University: Department of Electrical Engineering
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EE 435: Project One
Kyle Lichtenberg
Next the second stage was designed and implemented, shown in the following schematic:
From here, the common mode feedback circuit was designed based of off the schematic
given in class, and sized accordingly. This circuit could be very similar to that of the one
used in class since it would have little effect on the specifications that had to be met. The
circuit is shown on the following page:
Iowa State University: Department of Electrical Engineering
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EE 435: Project One
Kyle Lichtenberg
Last, the current generator was made, once again based off of the design given in class.
The current generated was around 9 μA, and this was done in order to account for small
changes in current. The circuit schematic is shown below:
Iowa State University: Department of Electrical Engineering
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EE 435: Project One
Kyle Lichtenberg
All of these pieces were then put together to form the two stage fully differential
operational amplifier. Next, the circuit had to be tested to ensure the various
specifications were met. The basic circuit used to test bench these specifications is shown
below. In some instances, a probe was added to the differential output.
The first specification tested was the gain, along with the gain bandwidth product. The
following plot confirms that the gain was above 100 dB (about 102.6 dB), and the gain
bandwidth product was above 30 MHz (about 32.5 MHz):
Iowa State University: Department of Electrical Engineering
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EE 435: Project One
Kyle Lichtenberg
Along with the gain, the phase was also recorded in order to achieve the entire bode plot:
Next, the slew rate was tested using a pulse. The following output was obtained for the
positive output, and a slew rate of 59.9 MV/s was obtained:
Iowa State University: Department of Electrical Engineering
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EE 435: Project One
Kyle Lichtenberg
The slew rate for the negative output was also tested and turned out to be about 56 MV/s.
The plot is shown below:
Next, the input common mode range was tested, and it seemed an error occurred in the
testing process, leaving the plot hard to read and understand. The plot is included below,
although no conclusive data could be derived:
Iowa State University: Department of Electrical Engineering
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EE 435: Project One
Kyle Lichtenberg
Following the input common mode range, the output swing range was tested. First the
positive output was tested, as the positive and negative outputs could not be swept
accurately on the same plot:
The output swing range of the negative output was then tested, and unpredictably
followed the same curve. The curve was expected to be mirrored, but if you mirror the
curve it would be easy to tell that the output swing range is in fact large:
Iowa State University: Department of Electrical Engineering
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EE 435: Project One
Kyle Lichtenberg
Last, the phase margin was tested and recorded. The following plot is that of the phase
margin:
From this plot, it can be concluded that the phase margin is about 50 degrees, well within
the specified range.
Conclusion
This project was a true test of the knowledge learned in the class thus far. Many problems
occurred throughout the project, mostly due to the strict specifications. When some parts
of the circuit were tweaked in order to enhance a specification, it would throw off the
value of another specification. A true medium had to be found in order to ensure the
specifications would be met. Also, new circuit elements had to be added for this project
increasing the complexity. Among these new elements was the common mode feedback
circuit, which was not needed in previous labs. Also, the current generator had to be
added, and while straightforward, offered more elements and power consumption
(although there was not limit on the power consumption for this project). Much was
learned throughout this project about analog circuit design, and the operation of circuits
and circuit elements as a whole.
Iowa State University: Department of Electrical Engineering
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