COCS 312
Course Name
Code/No
Computer Organization
COCS 312
Units
Lecture
Lab
Training
3
0
0
Credit Units
Prerequisite
3
COCS 203
Course Objectives:
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To understand how a CPU’s control unit interprets a machine-level instruction either directly or as a micro
program
To understand the difference between processor performance and system performance
To understand how computer performance is measured by measurements such as MIPS or SPEC marks and
the limitations of such measurements.
To understand how performance can be increased by incorporating multiple processors on a single chip.
To understand how special-purpose graphics processors, GPUs, can accelerate performance in graphics
applications
To understand the organization of computer structures that can be electronically configured and
reconfigured
Course Description:
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This course teaches the organization of the computer at the cache, and bus level. Students should also
understand the complex tradeoffs between CPU clock speed, cache size, bus organization and number of
core processors
Course Outline:
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Functional Organization
Review of register transfer language to describe internal operations in a computer
Micro architectures - hardwired and micro programmed realizations
Instruction pipelining and instruction-level parallelism (ILP)
Overview of superscalar architectures
Processor and system performance
Performance – their measures and their limitations
The significance of power dissipation and its effects on computing structures
Multiprocessing
Amdahl’s law
Short vector processing (multimedia operations)
Multi core and multithreaded processors
Flynn’s taxonomy: Multiprocessor structures and architectures
Programming multiprocessor systems
GPU and special-purpose graphics processors
Introduction to reconfigurable logic and special-purpose processors
Course Outcomes:
Upon finishing this course, the students should:
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Review of the use of register transfer language to describe internal operations in a computer
Understand how a CPU’s control unit interprets a machine-level instruction – either directly or as a micro
program.
Appreciate how processor performance can be improved by overlapping the execution of instruction by
pipelining.
Understand the difference between processor performance and system performance (i.e., the effects of
memory systems, buses and software on overall performance
Appreciate how superscalar architectures use multiple arithmetic units to execute more than one instruction
per clock cycle.
Understand how computer performance is measured by measurements such as MIPS or SPEC marks and
the limitations of such measurements.
Appreciate the relationship between power dissipation and computer performance and the need to minimize
power consumption in mobile applications.
Discuss the concept of parallel processing and the relationship between parallelism and performance.
Appreciate that multimedia values (e.g. 8-/16-bit audio and visual data) can be operated on in parallel in
64-bit registers to enhance performance.
Understand how performance can be increased by incorporating multiple processors on a single chip.
Appreciate the need to express algorithms in a form suitable for execution on parallel processors.
Understand how special-purpose graphics processors, GPUs, can accelerate performance in graphics
applications
Understand the organization of computer structures that can be electronically configured and reconfigured
Discuss the concept of parallel processing and the relationship between parallelism and performance.
Assessment Strategy:
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Students will be assessed in this course based on a set of exams, quizzes and practical parts of it.
Text Book:
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W. Stallings. "Computer Organization and Architecture: Designing for Performance ", 8th Ed., Prentice Hall,
2009, ISBN 0131856448
Other References:
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M. M. Mano, "Digital Design", 4th Edition, Prentice Hall, 2006, ISBN 0130621216.
C. H. Roth, "Fundamentals of Logic Design", 6th Ed., Thomson-Engineering, 2009, ISBN 0534378048
M. J. Murdocca and V. P. Heuring. "Principles of Computer Architecture", Prentice Hall, 1999, ISBN
0201436647.
Time table for distributing theoretical course contents
Week
1
2
Theoretical course contents
Introduction to Computer Organization
Review of register transfer language to describe internal operations in a
Remarks
computer
Micro architectures - hardwired and micro programmed realizations
Instruction pipelining and instruction-level parallelism (ILP)
Overview of superscalar architectures
Processor and system performance
Performance – their measures and their limitations
Exam 1
The significance of power dissipation and its effects on computing
structures
Amdahl’s law
Short vector processing (multimedia operations)
Multi core and multithreaded processors
Flynn’s taxonomy: Multiprocessor structures and architectures
3
4
5
6
7
8
9
10
11
12
13
14
15
Programming multiprocessor systems
GPU and special-purpose graphics processors
Introduction to reconfigurable logic and special-purpose processors
Final Exam
Grading:
Homework 1
Homework 2
Homework 3
Project
Exam 1
Exam 2
Final Exam
TOTAL
3
3
4
10
20
20
40
100
Exam 2