234 REDUCED INSTRUCTION SET COMPUTERS (RISCs) J. Hennessy, VLSI processor architecture, IEEE Trans. Comput., C-33(11), 1221 – 1246 (1984). J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann: San Mateo, San Francisco, CA, 1996. R. Kessler, The Alpha 21264 Microprocessor, IEEE Micro, Vol. 19, issue 2, 24 – 36 (1999). R. Kessler, E. McLellan and D. Webb, The Alpha 21264 Microprocessor Architecture, International Conference on Computer Design, Oct. 88, pp. 96 – 102. G. Lauthbatch and T. Horel, UltraSPARC-III: Designing third generation 64-bit performance, IEEE Micro., 73 – 85 (1999). R. Nair, Optimal 2-bit branch predictors, IEEE Trans. Comput., 698 (1995). D. Patterson, Reduced instruction set computers, Commun. ACM, 28(1), 8 – 21 (1985). D. Patterson and R. Ditzel, The case for the reduced instruction set computer, Comput. Architecture News, 8(6), 25 – 33 (1980). D. Patterson and C. Sequin, A VLSI RISC, IEEE Comput., 15(9), 8 – 21 (1982). G. Radin, The 801 minicomputer, IBM J. Res. Develop., 27(3), 237 – 246 (1983). R. Sherburne, M. Katevenis, D. Patterson and C. Sequin, A 32-bit NMOS processor with a large register file, IEEE J. Solid-State Circuits, Sc-19(5), 682 – 689 (1984). A. Tanenbaum, Structured Computer Organization, 3rd ed., Prentice-Hall: Englewood Cliffs, New Jersey. Websites http://www.sun.com/processors/UltraSPARC-IIIi http://www.sun.com/processors/whitepapers &CHAPTER 11 Introduction to Multiprocessors Having covered the essential issues in the design and analysis of uniprocessors and pointing out the main limitations of a single-stream machine, we begin in this chapter to pursue the issue of multiple processors. Here a number of processors (two or more) are connected in a manner that allows them to share the simultaneous execution of a single task. The main argument for using multiprocessors is to create powerful computers by simply connecting many existing smaller ones. A multiprocessor is expected to reach a faster speed than the fastest uniprocessor. In addition, a multiprocessor consisting of a number of single uniprocessors is expected to be more cost-effective than building a high-performance single processor. An additional advantage of a multiprocessor consisting of n processors is that if a single processor fails, the remaining fault-free n 2 1 processors should be able to provide continued service, albeit with degraded performance. Our coverage in this chapter starts with a section on the general concepts and terminology used. We then point to the different topologies used for interconnecting multiple processors. Different classification schemes for computer architectures are then introduced and analyzed. We then introduce a topology-based taxonomy for interconnection networks. Two memory-organization schemes for MIMD (multiple instruction multiple data) multiprocessors are also introduced. Our coverage in this chapter ends with a touch on the analysis and performance metrics for multiprocessors. It should be noted that interested readers are referred to more elaborate discussions on multiprocessors in Chapters 2 and 3 of our book on Advanced Computer Architecture and Parallel Processing (see reference list). 11.1. INTRODUCTION A multiple processor system consists of two or more processors that are connected in a manner that allows them to share the simultaneous (parallel) execution of a given computational task. Parallel processing has been advocated as a promising approach for building high-performance computer systems. Two basic requirements are inevitable for the efficient use of the employed processors. These requirements Fundamentals of Computer Organization and Architecture, by M. Abd-El-Barr and H. El-Rewini ISBN 0-471-46741-3 Copyright # 2005 John Wiley & Sons, Inc. 235