Power Aware BDD-based Logic Synthesis Using Adiabatic Multiplexers Sambhu N. Pradhan Gopal Paul Ajit Pal Bhargab B. Bhattacharya Dept. of Computer Sc. & Engg., IIT-Kharagpur ACMU, Indian Statistical Institute WB - 721302, India Kolkata - 700108, India sambhu.pradhan@gmail.com gpaulcal@yahoo.com apal@cse.iitkgp.ernet.in bhargab@isical.ac.in ABSTRACT Binary Decision Diagrams (BDDs) play an important role in the synthesis, verification, and testing of VLSI circuits. In this paper, we have proposed a new BDDbased approach for the synthesis of dual-rail adiabatic MUX circuits. The method yields around 22% reduction in the number of MUX blocks for several benchmark circuits compared to the conventional approach. Simulation result using SPICE on 180 nm technology shows, on an average, 50% reduction in power consumption for frequency ranging up to 300 MHz compared to implementation with static CMOS MUX circuits. At 600 MHz, power saving is observed to be nearly 35%. It is envisaged that the proposed approach will be useful in realizing low-power circuits. 1 INTRODUCTION A Binary Decision Diagram (BDD) [1] is a directed acyclic graph (DAG) that represents a Boolean function (or multiple functions) as a sum-of-disjointproducts (sodp) form. Not only BDDs provide an efficient data structure to represent Boolean functions, there is one-to-one correspondence between a BDD and a MUX-based realization of the function. So, the number of MUXs required to realize a function depends of the number of nodes in the BDD, which in turn depends on the ordering of variables. One popular package, known as CUDD [3], can be used to obtain an optimal-size BDD for a given function. However, in recent times, power consumption has been recognized as an important issue in implementing battery-operated portable devices. One of the techniques for designing low-power circuits and memory is to employ adiabatic logic that has received lot of attention recently [7,11, 13]. Design of an adiabatic ripple carry adder has been reported recently [10]. In this paper, we have presented a synthesis procedure for multi-output logic functions where, given its ROBDD, a pair of nodes with a certain property (called complementary pair) can be replaced by a single adiabatic MUX block. Hence, it not only helps in reducing the number of MUX blocks (by utilizing the dual-rail output of the adiabatic MUX), but also reduces power dissipation significantly by allowing recycling of energy to the power supply, a property intrinsic to adiabatic operations. The proposed technique will be useful in designing low-power portable devices [14] or biomedical implants that operate under a frequency of 600 MHz. 2 PRELIMINERIES The BDD corresponding to the full-adder function is shown in Fig. 1. The nodes of a BDD denote the variables of the function(s). Except for the two terminal nodes (labeled as 0 and 1), every node has exactly two outgoing edges drawn as solid and dashed lines corresponding to the decision value true or false of the node variable, respectively. The number of incoming edges on each node may be one or more. A BDD is called ordered (OBDD) if each variable appears at most once on each path from the root node to a terminal node, and if the variables appear in the same order in all other paths [2]. CUDD package [3] can be used to obtain an optimized ROBDD that can be directly mapped to adiabatic MUX-based logic circuits. Reduction of power dissipation in a system has become a very important issue with the proliferation of battery operated portable devices. Parameters like battery life, weight and size are used in an embedded/portable system are directly affected by power dissipation. The energy advantage can be readily understood by assuming a constant current source that delivers the charge CV over a time period T. The dissipation through the channel resistance R [12] is given by: 2 Ediss=PT = I2R T = CV R.T = RC .C.V 2 (1) T T Equation (1) shows that it is possible to charge and oppositely labeled incoming edges and 1(0)-successor discharge a capacitance through a resistance while dissipating less than CV2 of energy. It also suggests that it is possible to reduce the dissipation to an 1 SUM CARRY X1 X2 Y2 Y1 Z1 Y3 Y4 Z2 1 0 SUM = XYZ + XY Z + XYZ + XYZ + XYZ + XYZ + XYZ + XYZ; CARRY = XY + YZ + ZX. The two-output ROBDD graph for the variable ordering {X, Y, Z} is shown in Fig. 1. The solid edge (denoting label ‘1’) represents the true value of the corresponding variable, whereas, the dashed edge (denoting label ‘0’) represents the false value of the same. The leaf nodes denote the output value of the function. A complementary pair of nodes must correspond to the same variable; they should also have of a node should be 0(1) successor of the other. For example, {Y1, Y2} is a complementary pair and so is {Z1, Z2}. It is easy to map a BDD to a circuit using MUX [4]. MUX-based synthesis also offers many advantages from testability perspective. Figure 3 VPWR Fig. 1: BDD representation of a full adder arbitrary degree by increasing the switching time to ever-larger values. This principle is referred as the adiabatic charging. Several adiabatic logic families have been proposed so far. For better power management, logic families employing MOSFETs are preferred over diodes. The following three families are generally used: the Efficient Charge Recovery Logic (ECRL) [7], the 2N-2N2P [8], and the Positive Feedback Adiabatic Logic (PFAL) [9, 10]. It has been observed that the PFAL shows satisfactory performance in terms of energy consumption, useful frequency range, and robustness against technology parameter variations [11]. The energy dissipation of the adiabatic circuits is proportional to the square of the threshold voltage [12], given by: |Vtp| : Ediss = ½ C |Vtp|2 (2) Where Vtp is the threshold voltage of the transistor. Figure 2 shows the MUX circuit implemented with CMOS PFAL adiabatic logic. The logic output of both conventional and adiabatic MUX circuits is Vout, whereas in the adiabatic circuit an extra complementary output Vout is also present. In the case of conventional BDD, a complementary pair of nodes is synthesized by two MUX blocks as shown in Fig. 3. But the same can be implemented with single adiabatic MUX. Figure 4a shows a schematic dual-rail adiabatic MUX in contrast to a conventional MUX shown is Fig. 4b. a b a b s s s s F F Fig. 2: Schematic of an adiabatic MUX-block Fig. 3: Full adder synthesis by single-rail MUX blocks b a a b 1 3 BDD-BASED SYNTHESIS USING ADIABATIC MUX We will illustrate the procedure with a simple example. Consider the sum and carry functions of a 1-bit full adder, which are given by: s 0 F 0 1 F b a 1 s 0 F s F = as + bs F =as +bs F = as + bs b Fig. 4: aa) Adiabatic MUX, b) Conventional MUX 2 shows how the BDD of the full adder of Fig. 1 can be mapped to a conventional MUX-based circuit. Dreschsler et al. [5, 6] observed that a slight modification of a BDD-based MUX circuit could be made fully testable for all single stuck-at and pathdelay faults. The testability properties of a conventional MUX-based circuit will be preserved for an adiabatic MUX-based circuit too. Fig. 5 illustrates how the original BDD can be redrawn by collapsing complementary pairs. Each of these pairs can be replaced by a single adiabatic MUX block for technology mapping. Each of the remaining nodes will also need an adiabatic MUX, though not fully utilized. The final full adder circuit can be synthesized using adiabatic MUX blocks as shown in Fig. 6. This can be directly obtained from the BDD of Fig. 5. The dotted edges of Fig. 5 correspond to the complementary edges. Comparing Fig. 3 with Fig. 6, it may be observed that that number of MUX blocks is reduced from 8 to 6 in the case of adiabatic MUXbased realization. For large and complex circuits, this reduction can be significant. 4 RESULTS We have run the proposed algorithm on MCNC benchmark circuits [15] and observed considerable reduction in the number of BDD nodes after collapsing the complementary pairs. The reduced BDD is then mapped to PFAL-based adiabatic MUX blocks. Each adiabatic MUX is simulated using CADENCE SPECTRE SPICE on 180 nm technologies. With supply voltage of 1.8V and 500 random input patterns, the dissipated energy per cycle (in fJ) is calculated for both a conventional MUX and adiabatic MUX-based realizations. Figure 7 indicates a sample of input patterns applied to adiabatic MUX. The variation of 1 Z Y 0 1 0 0 1 1 0 F 0 1 Y F 1 0 0 1 F F 1 0 X 0 1 F F F’ F’ X 0 F F 1 0 1 1 0 F 0 Y 1 0 F F’ 0 1 F 1 F F’ SUM CARRY Fig. 6: Full adder synthesis using adiabatic MUX energy dissipated with operating frequency is shown in Fig. 8. For an adiabatic MUX, energy dissipation remains smaller compared to a conventional CMOS MUX until the crossover frequency is reached, which is observed to occur around 650 MHz. Next, for each benchmark circuit listed in Table 1, we compute the number of nodes in the modified BDD, and average power savings up to 300 MHz. Result shows, on an average, 22% reduction in number of MUX blocks and over 50% power consumption in the reduced BDDbased adiabatic circuit. Power consumption on interconnects is not considered here. Table-1 summarizes the results. For frequency up to 600 MHz, then power saving will reduce to nearly 35%. 5 CONCLUSION A novel approach for the synthesis of MUX-based adiabatic circuits has been presented in this paper. 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Wait Vpwr s s a a b b Fig. 8: Dissipated energy for adiabatic MUX and static CMOS MUX Fig. 7: Input signal patterns for adiabatic MUX Table-1: Comparative results for the conventional and adiabatic synthesis averaged up to 300 MHz No. of Reduction nodes in in nodes in the the modified modified BDD BDD 66 32.65% 6304 16.61% 40 28.57% 811 19.06% Avg. power Avg. power Reduction consump- consump-sion in power sion using using in CMOS adiabatic adiabatic MUX (nw) MUX (nw) MUX 79206.54 33885.72 57.22% 6110218.8 3236599.7 47.02% 45260.88 20536.8 54.62% 809846.46 416383.62 48.58% No. of outputs No. of nodes in the BDD No. of complementary pairs 35 33 8 45 16 25 8 45 98 7560 56 1002 32 1256 16 191 pcle 19 9 43 8 35 18.60% 34753.89 17969.7 48.29% t481 ttt2 vda x2 16 24 17 10 1 21 39 7 26 124 528 40 7 24 94 7 19 100 434 33 26.92% 19.35% 17.80% 17.50% 21013.98 100220.52 426745.44 32329.2 9754.98 51342 222824.28 16942.86 53.57% 48.77% 47.78% 40.59% Circuit name No. of inputs count 1908 f51m k2 4