COMPUTER ENGINEERING:
APPLICATIONS, INNOVATIONS,
AND CONTEMPORARY ISSUES
DR. MATTHEW MORRISON
DEPARTMENT OF ELECTRICAL ENGINEERING
UNIVERSITY OF MISSISSIPPI
OVERVIEW
• New Assistant Professor of Electrical Engineering
• Heading up new Computer Engineering Emphasis for MS and PhD Level
• VLSI System Design Research Laboratory
• Collaboration between High School and University Academics
• Contemporary Issues
• Smart Card Security
• Mitigating Differential Power Analysis Attacks
NEW COMPUTER ENGINEERING EMPHASIS
• Develop MS and PhD program in Computer Engineering
• Teaching Mission Statement: To develop Computer Engineering students academically,
creatively, and morally, and to engender ideals of integrity, professionalism, and lifelong
learning and teaching in order to graduate engineers who are dedicated to a career of
utilizing the principles of science for Humanity's benefit.
• Teaching Vision Statement: To develop outstanding Computer Engineers by imbuing
students with world-class study habits by combining Navy teaching methods with modern
engineering teaching tools.
OLE MISS VLSI SYSTEM DESIGN RESEARCH LAB
• Research Mission Statement: To perform research in Computer Engineering in
areas on CMOS/VLSI, Embedded Systems, Design Automation, and Hardware
Security.
• Research Vision Statement: To improve the security, safety,
reliability, and efficiency of computer architectures,
embedded systems, and application specific designs for the
benefit of humankind.
COLLABORATION WITH HS STUDENTS
• Objective: To provide summer research opportunities for exceptional juniors and senior high
school students in Mississippi through UM Outreach in collaboration with the Ole Miss Athletics
Department for the enhancement of the academic, athletic, and the physical and mental wellbeing of student athletes.
• Mission: Develop and seeking funding for a summer research camp/program for outstanding
self-selecting juniors and senior high school students who are interested in science,
mathematics, and computer engineering.
• Vision: For the program to be highly competitive that engenders state-wide enthusiasm in
outstanding students in the state for the enhancement of the state of Mississippi.
COMPUTER ENGINEERING CHALLENGES
• The NAE has identified these 14
Grand Challenges for Engineering
in the 21st Century. The Grand
Challenges are a call to action and
serve as a focal point for society's
attention to opportunities and
challenges affecting our quality of
life.
CONTEMPORARY ISSUES
• A Smart Card is
• Credit-card size plastic with an embedded
microprocessor
• “Secure” against malicious tampering
and monitoring
• Applications: Banking, Government (Military), Security, Transportation, SmartPhone SIM
Cards.
• In Europe, the proliferation of Smart Cards had led to their standardization.
•
Standardization => Easier for attackers to know their operation
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POWER ANALYSIS ATTACK => DYNAMIC POWER
ANALYSIS
• The effect of an individual key bit may be observed using DPA
• The peaks are the result of the single bit being propagated through the
circuit
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INTRODUCTION: COMPUTING REVERSIBILITY
• Quantum mechanics principles govern the physical limitations of computing
circuits and systems
• Quantum Reversibility: A unique set of probabilistic interactions between corpuscles,
where they reach every possible state and return to their initial state, achieving zero
entropy gain
• Reversible logic: Computing design methodology which uses the bijective nature of
quantum reversibility to reduce power consumption in circuits as best as possible.
•
Systems dissipate energy due to bit erasure within their interconnected primitive structures,
which is an important consideration as transistor density increases.
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INTRODUCTION: ADIABACITY IN COMPUTING
•
Quantum Adiabatic
•
•
A physical system remains in its instantaneous eigenstate if a given perturbation is acting on it
slowly enough and if there is a gap between the eigenvalue and the rest of the Hamiltonian's
spectrum.
“Adiabatic” Computing Systems
•
Reduces switching energy through the use of a ramp function instead of the faster switching
achieved in step functions.
•
Therefore, transistors may be used in adiabatic operation, despite being demonstrated as
lossy devices.
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INTRODUCTION: SEMANTICS
• Since the terms “Reversible” and “Adiabatic” have different meanings in pure
quantum physics and computing system, this leads to many conceptual errors.
• Example: Many CMOS “reversible” circuits use conventional inverters and diodes, which
are not physically reversible.
•
If this were true, then the designer would have created a perpetual motion machine.
• Misconceptions lead to significant debate, which slows research progress.
•
Relatively few synthesis algorithms and applications developed.
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ADIABATIC DYNAMIC DIFFERENTIAL LOGIC
• Proposed Universal PADDL Cell
ADIABATIC DYNAMIC DIFFERENTIAL LOGIC
PADDL Cell operation at 13.56 MHz.
PADDL Cell operation at 13.56 MHz
compared to NAND gate at 13.56
MHz
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ADIABATIC DYNAMIC DIFFERENTIAL LOGIC
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ADIABATIC DYNAMIC DIFFERENTIAL LOGIC
•
Dual-Rail Adiabatic Rijndael S-Box
•
•
Synthesized using presented algorithm
Requires 9612 transistors for encryption
• This is higher than most single or dual-rail encryption ciphers
•
However, since the device is physically bijective, the S-box may be used during the decryption
phase
•
•
•
•
Not possible without physical bijectivity
Other implementations require added
Only 512 transistors required for decryption for this method
Significantly reduces or negates area overhead for encryption
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DUAL-RAIL ADIABATIC SYNTHESIS
• High-Level Algorithm
ESPRESSO is advantageous to
QM Reduction for functions with
many input variables and with
only few care
terms defined
* The fewer the edges, the fewer
the “cares” in the boolean
minimization
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DUAL-RAIL ADIABATIC SYNTHESIS
• Synthesis for Full Adder
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DUAL-RAIL ADIABATIC SYNTHESIS
• Synthesis Flow for Proposed Algorithm
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DUAL RAIL ADIABATIC RIJNDAEL S-BOX
• Forward Operation
DUAL RAIL ADIABATIC RIJNDAEL S-BOX
• Reverse Operation
DUAL RAIL ADIABATIC RIJNDAEL S-BOX
• Hspice Simulation
• Power Waveform for All 256 Inputs at 13.56MHz and 90nm
• Power Waveform for 16 Random Inputs
DUAL RAIL ADIABATIC RIJNDAEL S-BOX
•
Hspice Simulations performed using the following at a variety of frequencies:
•
•
•
•
IBM: 0.13μm, 90nm, 65nm
PTM: 45nm, 32nm, 22nm
Significant improvements in Differential Power and Average Power
•
•
•
TSMC: 0.35μm, 0.25μm, 0.18μm
Improvement by 57% over previous best “Adiabatic” approach (CSSAL)
Improvement by a factor of 120 over previous best dual-rail approach.
Reduced trade off in area with hardware reuse
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FUTURE WORK
• Significant Opportunities for Future Research!
• Dual-Rail Adiabatic Memory
• Design of a Turing-Complete Dual-Rail Architecture
•
Incorporate Dynamic Information Flow Tracking for Multiple Levels of Security
• Application: Secure Reliable Cost-Effective Patient Identification in Hospital Settings Using
Adiabatic NFC Circuits
•
•
Use of Reversible Adiabatic Hardware for ID chips in hospital bracelets
RFID: Highly applicable for low power, low frequency security
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