Design and FPGA Implementation of a Perimeter Estimator
K Benkrid and D Crookes
School of Computer Science, The Queen’s University of Belfast, Belfast BT7 1NN, UK
(K.Benkrid, D.Crookes)@qub.ac.uk
Abstract
The measurement of perimeters, areas, centroids and other shape related parameters of planar objects from
their digitised images is an important task in computer vision systems. In this paper, we present a
formulation of a simple and relatively accurate algorithm for estimating an object’s perimeters which is
particularly suited to hardware implementation. Details of the algorithm’s implementation on a Xilinx
XC4000 FPGA are also given. The resulting circuit is very compact and achieves a throughput of 85
Million pixels per second, which corresponds to 324 frames per second for 512 x 512 images.
1. Introduction
Measurement of perimeters, areas, centroids and other shape related parameters of planar objects
is an important task in industrial computerised visions systems [1]. Such systems perform shape
analysis on digitised images, which result from the projection of the object on a square grid of
sensor array [2]. The resulting images’ pixels (see Figure 1.b) are binary depending on whether
the pixel centre belongs to the object or not [3].
(a)
(b)
Stepwise boundary
(c)
Figure 1. (a) Original object shape (b) Object shape after digitisation (discrete form)
(c) object contour with its stepwise boundary
We define the contour of a digitised object as a sequence of boundary pixels of the object (see
Figure 1.c). This contour is often represented by a chain code [4]. Another view of the object
contour is the line between the object pixels and the background (the ‘crack’). Encoding this line
(a sequence of horizontal and vertical pixel edges) yields what is usually called the crack code of
the digitised object boundary [1] (identified as the bold line in Figure 1.c). Clearly the length of
the latter contour is greater than the perimeter of the original object, especially for shapes with
many corners: hence the problem of finding an efficient and accurate perimeter estimator.
One way of estimating the perimeter of a digitised object [5] [6] is to measure the number
of vertical and horizontal cracks, and perform subsequent adjustments (e.g. take the number of
corners into consideration). This solution is not attractive for hardware implementation.
Another approach is to approximate the real object boundary more accurately, and
perform subsequent measurements on this approximated contour [7]. In particular, it is common
to represent the contour as a line passing through the centre of boundary pixels – i.e. as a
sequence of horizontal, vertical and diagonal links[8]. Area measurements must of course take
this into account, as this approach effectively shaves off a little of each boundary pixel of the
object. Assuming square pixels, the perimeter is then estimated by:
Perimeter = No. of horizontal & vertical links + (No. of diagonal links *
2)
In the following, we will present an alternative formulation of this algorithm which is particularly
suited to FPGA implementation.
2. The formulation of the algorithm
Consider a binary image ‘Im1’ containing only one object. Before measuring its perimeter, we
need first to find the perimeter. A simple method for identifying the boundary pixels is to perform
an ‘Erode’ operation on the image. The boundary pixels are those which were eroded, and can be
found by subtracting the result from the original image, as shown in Figure 2.
As stated earlier, a count of the number of pixel edges (the cracks) does not give an
accurate measure of the perimeter (because of corners and diagonal edges). Instead, we will take
the contour as a sequence of links between the centres of adjacent boundary pixels (see Im2 in
Figure 2). However, rather than focus on the links (each of which straddles two boundary pixels),
we will consider the individual contribution of each boundary pixel. This contribution depends on
the path which the contour follows through the pixel. Assuming a one-pixel wide perimeter, and
an aspect ratio of 1.0 (i.e. square pixels), we can classify each edge pixel’s contribution to the
perimeter into one of the following categories (or any of their rotations) [9]:
(a)
and
(b)
and
(c)
and
in which case the contribution of the pixel is C = 1.
in which case the contribution of the pixel is C =
2.
in which case the contribution of the pixel is C = (1+ 2 )/2.
Im1
Input image Im1
Erode(Im1)
Minimum
~
0
~
0
0
0
~
0
~
Erode
Neighbourhood
operation
Erode(Im1)
Im1
Image-Image
subtraction
Im2 = Im1-Erode(Im1)
Approximated
boundary
Im2 = Im1-Erode(Im1)
Figure 2. An edge finding algorithm for binary images
The perimeter is then given by:
Perimeter
= No. of (a) pixels * 1
+ No. of (b) pixels* 2
+ No. of (c) pixels * (1+
2 )/2
(Equation 1)
One way of classifying the contribution of edge pixels (assumed to be ‘1’ against a background of
‘0’s) is to convolve the whole binary image ‘Im2’ with the following window:
T = Im2 <convolve>
10
2
10
2
1
2
10
2
10
The result of this convolution at each pixel position enables the category of the corresponding
edge pixel to be deduced:
Result (T[i,j])
category
5 or 15 or 7 or 25 or 27 or 17
(a)
13 or 23
(c)
21 or 33
(b)
anything else
no contribution
Table 1. Classification of different convolution pixel results
The make up of these result pixels is shown in Figure 3.
T=5
T=5
T=5
T = 15
T=7
T = 25
T = 27
T = 17
(a)
T = 13
T = 13
T = 23
(b)
T = 21
T = 21
T = 33
(c)
Figure 3. Different possibilities for edge segments
The perimeter will then be given by:
Perimeter
=
+
+
count(T=5,15,7,25,27 or 17) * 1
count(T=21 or 33) Pixels* 2
count(T=13 or 23) * (1+ 2 )/2
For hardware implementation purposes, the coefficients will be approximated in binary to eight
binary places as follows:
1 = 1.000000002, (1+ 2 )/2  1.001101012 and 2  1.011010102.
A block structure of the whole operation is given by Figure 4.
Input image Im1
Additive -Minimum
~
0
~
0
0
0
Erode
~
0
~
Neighbourhood
operation
Erode(Im1)
Im1
Image-Image
subtraction
Mult-Accumulate
(convolution)
10
2
10
2
1
2
10
2
10
Im2 = Im1-Erode(Im1)
Neighbourhood
operation
T
T = 5, 15, 7, 25,
17 or 27?
Binary image
Bin1
T = 13 or 23?
T = 21 or 33?
Binary image
Bin2
A1
Binary image
Bin3
A22
O = A1 * 1 + A2 *
A3
2
+ A3 * (1+
)/2
O
2
Im3 = Bin1 * 1 + Bin2 *
2
+ Bin3 * (1+
Global
accumulation
Perimeter =  Im 3[i, j ]
i, j
Figure 4. A block diagram of the proposed perimeter estimator
)/2
3. FPGA implementation
The above algorithm has been implemented on Xilinx XC4036EX-2 series [10] which consists of
a grid of 36x36 CLBs. Both ‘Erode’ and convolution 3x3 neighbourhood operations store two
lines of data on chip in order to supply each image pixel only once to the FPGA. Line buffers are
implemented efficiently using the distributed synchronous RAMs and a simple address counter.
Each CLB can hold up to 34 bits (i.e. pixels). Since the input of both operations is a binary
image, large line buffers can be readily stored on the chip.
The maximum possible result pixel value from the convolution operation is theoretically
49, which occurs when all the image pixel values within the 3x3 neighbourhood are 1. Hence, the
output pixel word length is 6 (49 = 1100012).
Each of the three ‘=’ units will output ‘1’ whenever its input (the convolution result) is
one of a set of particular constants (e.g. {13, 23}). Since the output of the convolution is 6 bits
wide, this implements a 6-input boolean function which can be implemented easily using the
XC4000 CLB’s look up tables. The corresponding area is hence independent of the number of
constants in any of the sets. The unit that implements Equation 1 receives 3 binary inputs and will
output the proper approximated coefficient values (for 1, 2 or (1+ 2 )/2) in bit parallel. This
can be seen as a multi-output boolean function that can again be easily implemented using the
XC4000 CLB’s look up tables. Finally, these pixel contributions are serially accumulated. The
accumulation is in bit parallel and is implemented using dedicated fast carry logic.
The whole circuit has been generated from a high level Hardware Description Notation
developed at Queen’s University called HIDE [11, 12]. A floorplan of the resulting architecture
for 512x512 input binary image on XC4036EX-2 is presented in Figure 5. The whole circuit
occupies 199 CLBs. This is 15% of the whole chip area. The remaining 85% is available to
implement other operations on the digitised input image (e.g. initial threshing if necessary, or area
centroid, or compactness estimation). Timing simulation shows that the circuit can run at 85MHz
which gives 85 Million pixel per second throughput.
Erode Convolution Accumulator
Input
Output
Line buffers
Figure 5. Physical configuration of ‘Perimeter estimator’ operation on XC4036EX-2
4. Conclusion
In this paper, we have presented a hardware implementation of an algorithm for perimeter
estimation. The standard algorithm has been reformulated to suit hardware implementation, and
offers a simple and relatively accurate way of estimating object perimeters. The resulting FPGA
implementation on a Xilinx XC4000 is very compact and achieves a maximum throughput of 85
Million pixels per second. This makes a suitable component for applications such as real time
object recognition. As it stands, there are several limitations on its application (e.g. only one
object in the image, the object must not have any holes). In practice, full application of the
presented unit for object recognition – perhaps based on measuring compactness – would need
surrounding components, e.g. to remove noise, and to calculate area. These can be incorporated
into a hardware solution without significant difficulty.
5. References
[1]
Rosenfeld A, and Kak A C, Digital Picture Processing. New York: Academic, pp. 310314, 1976.
[2] Rink M, “A computerized quatitative image analysis procedure for invistigating features
and an adapted image process”, J. Microscopy, vol. 107, pp. 267-286, 1976.
[3] Kulpa Z, “Area and perimeter measurement of bolbs in discrete binary pictures”,
Computer Graphics Image Processing, vol. 6, pp. 434-451, 1977.
[4] Freeman H, “Computer processing of line drawing images”, Comput. Surveys, vol. 6, pp.
57-97, 1974.
[5] Profitt D and Rosen D, “Metrication errors and coding efficiency of chain coding schemes
for the representation of lines and edges”, Computer Graphics Image Processing, vol. 10,
pp. 318-332, 1979.
[6] Koplowitz J and Bruckstein A M, “Design of Perimeter Estimators for Digitized Planar
Shapes”, IEEE transactions on Pattern Analysis and Machine Intelligence. Vol. PAMI(11),
pp. 611-622, 1989.
[7] Montanari U, “A note on minimal length polygonal approximation to a digitized contour”,
Communications ACM, vol. 13, pp. 41-46, 1970.
[8] Castleman K R, ‘Digital Image Processing’, Prentice Hall, 1996.
[9] Crookes D, “Image Processing”, Course Notes, School of Computer Science, The Queen’s
University of Belfast.
[10] http://www.xilinx.com/partinfo/4kconf.pdf
[11] Crookes D, Alotaibi K, Bouridane A, Donachy P and Benkrid A, ‘An Environment for
Generating FPGA Architectures for Image Algebra-based Algorithms’, ICIP98, Vol.3, pp
990-994. 1998.
[12] K Benkrid, D Crookes, A Bouridane, P Corr and KAlotaibi, ‘A High Level Software
Environment for FPGA Based Image Processing’, Proceedings IPA 99’, Manchester,
pp.112-116, 1999.